#ifndef __MACH_MESON6_REG_ADDR_H_
#define __MACH_MESON6_REG_ADDR_H_
#define P_SECOND_DEMUX_OFFSET_0 		CBUS_REG_ADDR(SECOND_DEMUX_OFFSET_0)
#define P_THIRD_DEMUX_OFFSET_0 		CBUS_REG_ADDR(THIRD_DEMUX_OFFSET_0)
#define P_STB_TOP_CONFIG 		CBUS_REG_ADDR(STB_TOP_CONFIG)
#define P_TS_TOP_CONFIG 		CBUS_REG_ADDR(TS_TOP_CONFIG)
#define P_TS_FILE_CONFIG 		CBUS_REG_ADDR(TS_FILE_CONFIG)
#define P_TS_PL_PID_INDEX 		CBUS_REG_ADDR(TS_PL_PID_INDEX)
#define P_TS_PL_PID_DATA 		CBUS_REG_ADDR(TS_PL_PID_DATA)
#define P_COMM_DESC_KEY0 		CBUS_REG_ADDR(COMM_DESC_KEY0)
#define P_COMM_DESC_KEY1 		CBUS_REG_ADDR(COMM_DESC_KEY1)
#define P_COMM_DESC_KEY_RW 		CBUS_REG_ADDR(COMM_DESC_KEY_RW)
#define P_PREG_CTLREG0_ADDR 		CBUS_REG_ADDR(PREG_CTLREG0_ADDR)
#define P_PREG_PAD_GPIO6_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO6_EN_N)
#define P_PREG_PAD_GPIO6_O 		CBUS_REG_ADDR(PREG_PAD_GPIO6_O)
#define P_PREG_PAD_GPIO6_I 		CBUS_REG_ADDR(PREG_PAD_GPIO6_I)
#define P_PREG_JTAG_GPIO_ADDR 		CBUS_REG_ADDR(PREG_JTAG_GPIO_ADDR)
#define P_PREG_PAD_GPIO0_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO0_EN_N)
#define P_PREG_PAD_GPIO0_O 		CBUS_REG_ADDR(PREG_PAD_GPIO0_O)
#define P_PREG_PAD_GPIO0_I 		CBUS_REG_ADDR(PREG_PAD_GPIO0_I)
#define P_PREG_PAD_GPIO1_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO1_EN_N)
#define P_PREG_PAD_GPIO1_O 		CBUS_REG_ADDR(PREG_PAD_GPIO1_O)
#define P_PREG_PAD_GPIO1_I 		CBUS_REG_ADDR(PREG_PAD_GPIO1_I)
#define P_PREG_PAD_GPIO2_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N)
#define P_PREG_PAD_GPIO2_O 		CBUS_REG_ADDR(PREG_PAD_GPIO2_O)
#define P_PREG_PAD_GPIO2_I 		CBUS_REG_ADDR(PREG_PAD_GPIO2_I)
#define P_PREG_PAD_GPIO3_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO3_EN_N)
#define P_PREG_PAD_GPIO3_O 		CBUS_REG_ADDR(PREG_PAD_GPIO3_O)
#define P_PREG_PAD_GPIO3_I 		CBUS_REG_ADDR(PREG_PAD_GPIO3_I)
#define P_PREG_PAD_GPIO4_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO4_EN_N)
#define P_PREG_PAD_GPIO4_O 		CBUS_REG_ADDR(PREG_PAD_GPIO4_O)
#define P_PREG_PAD_GPIO4_I 		CBUS_REG_ADDR(PREG_PAD_GPIO4_I)
#define P_PREG_PAD_GPIO5_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO5_EN_N)
#define P_PREG_PAD_GPIO5_O 		CBUS_REG_ADDR(PREG_PAD_GPIO5_O)
#define P_PREG_PAD_GPIO5_I 		CBUS_REG_ADDR(PREG_PAD_GPIO5_I)
#define P_A9_CFG0 		CBUS_REG_ADDR(A9_CFG0)
#define P_A9_CFG1 		CBUS_REG_ADDR(A9_CFG1)
#define P_A9_CFG2 		CBUS_REG_ADDR(A9_CFG2)
#define P_A9_PERIPH_BASE 		CBUS_REG_ADDR(A9_PERIPH_BASE)
#define P_A9_L2_REG_BASE 		CBUS_REG_ADDR(A9_L2_REG_BASE)
#define P_A9_L2_STATUS 		CBUS_REG_ADDR(A9_L2_STATUS)
#define P_A9_POR_CFG 		CBUS_REG_ADDR(A9_POR_CFG)
#define P_MALI_IDLE_STAT 		CBUS_REG_ADDR(MALI_IDLE_STAT)
#define P_AXI_REG_EN 		CBUS_REG_ADDR(AXI_REG_EN)
#define P_PERIPHS_PIN_MUX_0 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_0)
#define P_PERIPHS_PIN_MUX_1 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
#define P_PERIPHS_PIN_MUX_2 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
#define P_PERIPHS_PIN_MUX_3 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
#define P_PERIPHS_PIN_MUX_4 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_4)
#define P_PERIPHS_PIN_MUX_5 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
#define P_PERIPHS_PIN_MUX_6 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_6)
#define P_PERIPHS_PIN_MUX_7 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
#define P_PERIPHS_PIN_MUX_8 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_8)
#define P_PERIPHS_PIN_MUX_9 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_9)
#define P_PERIPHS_PIN_MUX_10 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_10)
#define P_PERIPHS_PIN_MUX_11 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_11)
#define P_PERIPHS_PIN_MUX_12 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_12)
#define P_PAD_PULL_UP_REG6 		CBUS_REG_ADDR(PAD_PULL_UP_REG6)
#define P_PAD_PULL_UP_REG0 		CBUS_REG_ADDR(PAD_PULL_UP_REG0)
#define P_PAD_PULL_UP_REG1 		CBUS_REG_ADDR(PAD_PULL_UP_REG1)
#define P_PAD_PULL_UP_REG2 		CBUS_REG_ADDR(PAD_PULL_UP_REG2)
#define P_PAD_PULL_UP_REG3 		CBUS_REG_ADDR(PAD_PULL_UP_REG3)
#define P_PAD_PULL_UP_REG4 		CBUS_REG_ADDR(PAD_PULL_UP_REG4)
#define P_PAD_PULL_UP_REG5 		CBUS_REG_ADDR(PAD_PULL_UP_REG5)
#define P_RAND64_ADDR0 		CBUS_REG_ADDR(RAND64_ADDR0)
#define P_RAND64_ADDR1 		CBUS_REG_ADDR(RAND64_ADDR1)
#define P_PREG_ETHERNET_ADDR0 		CBUS_REG_ADDR(PREG_ETHERNET_ADDR0)
#define P_PREG_AM_ANALOG_ADDR 		CBUS_REG_ADDR(PREG_AM_ANALOG_ADDR)
#define P_PREG_MALI_BYTE_CNTL 		CBUS_REG_ADDR(PREG_MALI_BYTE_CNTL)
#define P_PREG_WIFI_CNTL 		CBUS_REG_ADDR(PREG_WIFI_CNTL)
#define P_AM_ANALOG_TOP_REG0 		CBUS_REG_ADDR(AM_ANALOG_TOP_REG0)
#define P_AM_ANALOG_TOP_REG1 		CBUS_REG_ADDR(AM_ANALOG_TOP_REG1)
#define P_PREG_STICKY_REG0 		CBUS_REG_ADDR(PREG_STICKY_REG0)
#define P_PREG_STICKY_REG1 		CBUS_REG_ADDR(PREG_STICKY_REG1)
#define P_PREG_MV_REG 		CBUS_REG_ADDR(PREG_MV_REG)
#define P_AM_RING_OSC_REG0 		CBUS_REG_ADDR(AM_RING_OSC_REG0)
#define P_USB_ADDR0 		CBUS_REG_ADDR(USB_ADDR0)
#define P_USB_ADDR1 		CBUS_REG_ADDR(USB_ADDR1)
#define P_USB_ADDR2 		CBUS_REG_ADDR(USB_ADDR2)
#define P_USB_ADDR3 		CBUS_REG_ADDR(USB_ADDR3)
#define P_USB_ADDR4 		CBUS_REG_ADDR(USB_ADDR4)
#define P_USB_ADDR5 		CBUS_REG_ADDR(USB_ADDR5)
#define P_USB_ADDR6 		CBUS_REG_ADDR(USB_ADDR6)
#define P_USB_ADDR7 		CBUS_REG_ADDR(USB_ADDR7)
#define P_USB_ADDR8 		CBUS_REG_ADDR(USB_ADDR8)
#define P_USB_ADDR9 		CBUS_REG_ADDR(USB_ADDR9)
#define P_USB_ADDR10 		CBUS_REG_ADDR(USB_ADDR10)
#define P_USB_ADDR11 		CBUS_REG_ADDR(USB_ADDR11)
#define P_USB_ADDR12 		CBUS_REG_ADDR(USB_ADDR12)
#define P_USB_ADDR13 		CBUS_REG_ADDR(USB_ADDR13)
#define P_USB_ADDR14 		CBUS_REG_ADDR(USB_ADDR14)
#define P_USB_ADDR15 		CBUS_REG_ADDR(USB_ADDR15)
#define P_SMARTCARD_REG0 		CBUS_REG_ADDR(SMARTCARD_REG0)
#define P_SMARTCARD_REG1 		CBUS_REG_ADDR(SMARTCARD_REG1)
#define P_SMARTCARD_REG2 		CBUS_REG_ADDR(SMARTCARD_REG2)
#define P_SMARTCARD_STATUS 		CBUS_REG_ADDR(SMARTCARD_STATUS)
#define P_SMARTCARD_INTR 		CBUS_REG_ADDR(SMARTCARD_INTR)
#define P_SMARTCARD_REG5 		CBUS_REG_ADDR(SMARTCARD_REG5)
#define P_SMARTCARD_REG6 		CBUS_REG_ADDR(SMARTCARD_REG6)
#define P_SMARTCARD_FIFO 		CBUS_REG_ADDR(SMARTCARD_FIFO)
#define P_IR_DEC_LDR_ACTIVE 		CBUS_REG_ADDR(IR_DEC_LDR_ACTIVE)
#define P_IR_DEC_LDR_IDLE 		CBUS_REG_ADDR(IR_DEC_LDR_IDLE)
#define P_IR_DEC_LDR_REPEAT 		CBUS_REG_ADDR(IR_DEC_LDR_REPEAT)
#define P_IR_DEC_BIT_0 		CBUS_REG_ADDR(IR_DEC_BIT_0)
#define P_IR_DEC_REG0 		CBUS_REG_ADDR(IR_DEC_REG0)
#define P_IR_DEC_FRAME 		CBUS_REG_ADDR(IR_DEC_FRAME)
#define P_IR_DEC_STATUS 		CBUS_REG_ADDR(IR_DEC_STATUS)
#define P_IR_DEC_REG1 		CBUS_REG_ADDR(IR_DEC_REG1)
#define P_DEMOD_ADC_SAMPLING 		CBUS_REG_ADDR(DEMOD_ADC_SAMPLING)
#define P_UART0_WFIFO 		CBUS_REG_ADDR(UART0_WFIFO)
#define P_UART0_RFIFO 		CBUS_REG_ADDR(UART0_RFIFO)
#define P_UART0_CONTROL 		CBUS_REG_ADDR(UART0_CONTROL)
#define P_UART0_STATUS 		CBUS_REG_ADDR(UART0_STATUS)
#define P_UART0_MISC 		CBUS_REG_ADDR(UART0_MISC)
#define P_UART0_REG5 		CBUS_REG_ADDR(UART0_REG5)
#define P_UART1_WFIFO 		CBUS_REG_ADDR(UART1_WFIFO)
#define P_UART1_RFIFO 		CBUS_REG_ADDR(UART1_RFIFO)
#define P_UART1_CONTROL 		CBUS_REG_ADDR(UART1_CONTROL)
#define P_UART1_STATUS 		CBUS_REG_ADDR(UART1_STATUS)
#define P_UART1_MISC 		CBUS_REG_ADDR(UART1_MISC)
#define P_UART1_REG5 		CBUS_REG_ADDR(UART1_REG5)
#define P_I2C_M_0_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_0_CONTROL_REG)
#define P_I2C_M_0_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_0_SLAVE_ADDR)
#define P_I2C_M_0_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST0)
#define P_I2C_M_0_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST1)
#define P_I2C_M_0_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_0_WDATA_REG0)
#define P_I2C_M_0_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_0_WDATA_REG1)
#define P_I2C_M_0_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_0_RDATA_REG0)
#define P_I2C_M_0_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_0_RDATA_REG1)
#define P_I2C_S_CONTROL_REG 		CBUS_REG_ADDR(I2C_S_CONTROL_REG)
#define P_I2C_S_SEND_REG 		CBUS_REG_ADDR(I2C_S_SEND_REG)
#define P_I2C_S_RECV_REG 		CBUS_REG_ADDR(I2C_S_RECV_REG)
#define P_I2C_S_CNTL1_REG 		CBUS_REG_ADDR(I2C_S_CNTL1_REG)
#define P_PWM_PWM_A 		CBUS_REG_ADDR(PWM_PWM_A)
#define P_PWM_PWM_B 		CBUS_REG_ADDR(PWM_PWM_B)
#define P_PWM_MISC_REG_AB 		CBUS_REG_ADDR(PWM_MISC_REG_AB)
#define P_PWM_DELTA_SIGMA_AB 		CBUS_REG_ADDR(PWM_DELTA_SIGMA_AB)
#define P_ATAPI_IDEREG0 		CBUS_REG_ADDR(ATAPI_IDEREG0)
#define P_ATAPI_IDEREG1 		CBUS_REG_ADDR(ATAPI_IDEREG1)
#define P_ATAPI_IDEREG2 		CBUS_REG_ADDR(ATAPI_IDEREG2)
#define P_ATAPI_CYCTIME 		CBUS_REG_ADDR(ATAPI_CYCTIME)
#define P_ATAPI_IDETIME 		CBUS_REG_ADDR(ATAPI_IDETIME)
#define P_ATAPI_PIO_TIMING 		CBUS_REG_ADDR(ATAPI_PIO_TIMING)
#define P_ATAPI_TABLE_ADD_REG 		CBUS_REG_ADDR(ATAPI_TABLE_ADD_REG)
#define P_ATAPI_IDEREG3 		CBUS_REG_ADDR(ATAPI_IDEREG3)
#define P_ATAPI_UDMA_REG0 		CBUS_REG_ADDR(ATAPI_UDMA_REG0)
#define P_ATAPI_UDMA_REG1 		CBUS_REG_ADDR(ATAPI_UDMA_REG1)
#define P_TRANS_PWMA_REG0 		CBUS_REG_ADDR(TRANS_PWMA_REG0)
#define P_TRANS_PWMA_REG1 		CBUS_REG_ADDR(TRANS_PWMA_REG1)
#define P_TRANS_PWMA_MUX0 		CBUS_REG_ADDR(TRANS_PWMA_MUX0)
#define P_TRANS_PWMA_MUX1 		CBUS_REG_ADDR(TRANS_PWMA_MUX1)
#define P_TRANS_PWMA_MUX2 		CBUS_REG_ADDR(TRANS_PWMA_MUX2)
#define P_TRANS_PWMA_MUX3 		CBUS_REG_ADDR(TRANS_PWMA_MUX3)
#define P_TRANS_PWMA_MUX4 		CBUS_REG_ADDR(TRANS_PWMA_MUX4)
#define P_TRANS_PWMA_MUX5 		CBUS_REG_ADDR(TRANS_PWMA_MUX5)
#define P_TRANS_PWMB_REG0 		CBUS_REG_ADDR(TRANS_PWMB_REG0)
#define P_TRANS_PWMB_REG1 		CBUS_REG_ADDR(TRANS_PWMB_REG1)
#define P_TRANS_PWMB_MUX0 		CBUS_REG_ADDR(TRANS_PWMB_MUX0)
#define P_TRANS_PWMB_MUX1 		CBUS_REG_ADDR(TRANS_PWMB_MUX1)
#define P_TRANS_PWMB_MUX2 		CBUS_REG_ADDR(TRANS_PWMB_MUX2)
#define P_TRANS_PWMB_MUX3 		CBUS_REG_ADDR(TRANS_PWMB_MUX3)
#define P_TRANS_PWMB_MUX4 		CBUS_REG_ADDR(TRANS_PWMB_MUX4)
#define P_TRANS_PWMB_MUX5 		CBUS_REG_ADDR(TRANS_PWMB_MUX5)
#define P_NAND_START 		CBUS_REG_ADDR(NAND_START)
#define P_NAND_ADR_CMD 		CBUS_REG_ADDR(NAND_ADR_CMD)
#define P_NAND_ADR_STS 		CBUS_REG_ADDR(NAND_ADR_STS)
#define P_NAND_END 		CBUS_REG_ADDR(NAND_END)
#define P_PWM_PWM_C 		CBUS_REG_ADDR(PWM_PWM_C)
#define P_PWM_PWM_D 		CBUS_REG_ADDR(PWM_PWM_D)
#define P_PWM_MISC_REG_CD 		CBUS_REG_ADDR(PWM_MISC_REG_CD)
#define P_PWM_DELTA_SIGMA_CD 		CBUS_REG_ADDR(PWM_DELTA_SIGMA_CD)
#define P_SAR_ADC_REG0 		CBUS_REG_ADDR(SAR_ADC_REG0)
#define P_SAR_ADC_CHAN_LIST 		CBUS_REG_ADDR(SAR_ADC_CHAN_LIST)
#define P_SAR_ADC_AVG_CNTL 		CBUS_REG_ADDR(SAR_ADC_AVG_CNTL)
#define P_SAR_ADC_REG3 		CBUS_REG_ADDR(SAR_ADC_REG3)
#define P_SAR_ADC_DELAY 		CBUS_REG_ADDR(SAR_ADC_DELAY)
#define P_SAR_ADC_LAST_RD 		CBUS_REG_ADDR(SAR_ADC_LAST_RD)
#define P_SAR_ADC_FIFO_RD 		CBUS_REG_ADDR(SAR_ADC_FIFO_RD)
#define P_SAR_ADC_AUX_SW 		CBUS_REG_ADDR(SAR_ADC_AUX_SW)
#define P_SAR_ADC_CHAN_10_SW 		CBUS_REG_ADDR(SAR_ADC_CHAN_10_SW)
#define P_SAR_ADC_DETECT_IDLE_SW 		CBUS_REG_ADDR(SAR_ADC_DETECT_IDLE_SW)
#define P_SAR_ADC_DELTA_10 		CBUS_REG_ADDR(SAR_ADC_DELTA_10)
#define P_CTOUCH_REG0 		CBUS_REG_ADDR(CTOUCH_REG0)
#define P_CTOUCH_REG1 		CBUS_REG_ADDR(CTOUCH_REG1)
#define P_CTOUCH_FIFO 		CBUS_REG_ADDR(CTOUCH_FIFO)
#define P_CTOUCH_REG3 		CBUS_REG_ADDR(CTOUCH_REG3)
#define P_CTOUCH_INIT_CLK0 		CBUS_REG_ADDR(CTOUCH_INIT_CLK0)
#define P_CTOUCH_INIT_CLK1 		CBUS_REG_ADDR(CTOUCH_INIT_CLK1)
#define P_CTOUCH_REG6 		CBUS_REG_ADDR(CTOUCH_REG6)
#define P_CTOUCH_GND_SW_MASK 		CBUS_REG_ADDR(CTOUCH_GND_SW_MASK)
#define P_CTOUCH_MSR_TB_SEL 		CBUS_REG_ADDR(CTOUCH_MSR_TB_SEL)
#define P_CTOUCH_CAP_THRESH0 		CBUS_REG_ADDR(CTOUCH_CAP_THRESH0)
#define P_CTOUCH_CAP_THRESH1 		CBUS_REG_ADDR(CTOUCH_CAP_THRESH1)
#define P_CTOUCH_CHAN_LIST0 		CBUS_REG_ADDR(CTOUCH_CHAN_LIST0)
#define P_CTOUCH_CHAN_LIST1 		CBUS_REG_ADDR(CTOUCH_CHAN_LIST1)
#define P_CTOUCH_MSR_TB0 		CBUS_REG_ADDR(CTOUCH_MSR_TB0)
#define P_CTOUCH_MSR_TB1 		CBUS_REG_ADDR(CTOUCH_MSR_TB1)
#define P_CTOUCH_REG15 		CBUS_REG_ADDR(CTOUCH_REG15)
#define P_UART2_WFIFO 		CBUS_REG_ADDR(UART2_WFIFO)
#define P_UART2_RFIFO 		CBUS_REG_ADDR(UART2_RFIFO)
#define P_UART2_CONTROL 		CBUS_REG_ADDR(UART2_CONTROL)
#define P_UART2_STATUS 		CBUS_REG_ADDR(UART2_STATUS)
#define P_UART2_MISC 		CBUS_REG_ADDR(UART2_MISC)
#define P_UART2_REG5 		CBUS_REG_ADDR(UART2_REG5)
#define P_UART3_WFIFO 		CBUS_REG_ADDR(UART3_WFIFO)
#define P_UART3_RFIFO 		CBUS_REG_ADDR(UART3_RFIFO)
#define P_UART3_CONTROL 		CBUS_REG_ADDR(UART3_CONTROL)
#define P_UART3_STATUS 		CBUS_REG_ADDR(UART3_STATUS)
#define P_UART3_MISC 		CBUS_REG_ADDR(UART3_MISC)
#define P_UART3_REG5 		CBUS_REG_ADDR(UART3_REG5)
#define P_RTC_ADDR0 		CBUS_REG_ADDR(RTC_ADDR0)
#define P_RTC_ADDR1 		CBUS_REG_ADDR(RTC_ADDR1)
#define P_RTC_ADDR2 		CBUS_REG_ADDR(RTC_ADDR2)
#define P_RTC_ADDR3 		CBUS_REG_ADDR(RTC_ADDR3)
#define P_RTC_ADDR4 		CBUS_REG_ADDR(RTC_ADDR4)
#define P_MSR_CLK_DUTY 		CBUS_REG_ADDR(MSR_CLK_DUTY)
#define P_MSR_CLK_REG0 		CBUS_REG_ADDR(MSR_CLK_REG0)
#define P_MSR_CLK_REG1 		CBUS_REG_ADDR(MSR_CLK_REG1)
#define P_MSR_CLK_REG2 		CBUS_REG_ADDR(MSR_CLK_REG2)
#define P_LED_PWM_REG0 		CBUS_REG_ADDR(LED_PWM_REG0)
#define P_LED_PWM_REG1 		CBUS_REG_ADDR(LED_PWM_REG1)
#define P_LED_PWM_REG2 		CBUS_REG_ADDR(LED_PWM_REG2)
#define P_LED_PWM_REG3 		CBUS_REG_ADDR(LED_PWM_REG3)
#define P_LED_PWM_REG4 		CBUS_REG_ADDR(LED_PWM_REG4)
#define P_LED_PWM_REG5 		CBUS_REG_ADDR(LED_PWM_REG5)
#define P_LED_PWM_REG6 		CBUS_REG_ADDR(LED_PWM_REG6)
#define P_VGHL_PWM_REG0 		CBUS_REG_ADDR(VGHL_PWM_REG0)
#define P_VGHL_PWM_REG1 		CBUS_REG_ADDR(VGHL_PWM_REG1)
#define P_VGHL_PWM_REG2 		CBUS_REG_ADDR(VGHL_PWM_REG2)
#define P_VGHL_PWM_REG3 		CBUS_REG_ADDR(VGHL_PWM_REG3)
#define P_VGHL_PWM_REG4 		CBUS_REG_ADDR(VGHL_PWM_REG4)
#define P_VGHL_PWM_REG5 		CBUS_REG_ADDR(VGHL_PWM_REG5)
#define P_VGHL_PWM_REG6 		CBUS_REG_ADDR(VGHL_PWM_REG6)
#define P_I2C_M_1_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_1_CONTROL_REG)
#define P_I2C_M_1_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_1_SLAVE_ADDR)
#define P_I2C_M_1_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST0)
#define P_I2C_M_1_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST1)
#define P_I2C_M_1_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_1_WDATA_REG0)
#define P_I2C_M_1_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_1_WDATA_REG1)
#define P_I2C_M_1_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_1_RDATA_REG0)
#define P_I2C_M_1_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_1_RDATA_REG1)
#define P_I2C_M_2_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_2_CONTROL_REG)
#define P_I2C_M_2_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_2_SLAVE_ADDR)
#define P_I2C_M_2_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST0)
#define P_I2C_M_2_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST1)
#define P_I2C_M_2_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_2_WDATA_REG0)
#define P_I2C_M_2_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_2_WDATA_REG1)
#define P_I2C_M_2_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_2_RDATA_REG0)
#define P_I2C_M_2_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_2_RDATA_REG1)
#define P_BT_CTRL 		CBUS_REG_ADDR(BT_CTRL)
#define P_BT_VBISTART 		CBUS_REG_ADDR(BT_VBISTART)
#define P_BT_VBIEND 		CBUS_REG_ADDR(BT_VBIEND)
#define P_BT_FIELDSADR 		CBUS_REG_ADDR(BT_FIELDSADR)
#define P_BT_LINECTRL 		CBUS_REG_ADDR(BT_LINECTRL)
#define P_BT_VIDEOSTART 		CBUS_REG_ADDR(BT_VIDEOSTART)
#define P_BT_VIDEOEND 		CBUS_REG_ADDR(BT_VIDEOEND)
#define P_BT_SLICELINE0 		CBUS_REG_ADDR(BT_SLICELINE0)
#define P_BT_SLICELINE1 		CBUS_REG_ADDR(BT_SLICELINE1)
#define P_BT_PORT_CTRL 		CBUS_REG_ADDR(BT_PORT_CTRL)
#define P_BT_SWAP_CTRL 		CBUS_REG_ADDR(BT_SWAP_CTRL)
#define P_BT_ANCISADR 		CBUS_REG_ADDR(BT_ANCISADR)
#define P_BT_ANCIEADR 		CBUS_REG_ADDR(BT_ANCIEADR)
#define P_BT_AFIFO_CTRL 		CBUS_REG_ADDR(BT_AFIFO_CTRL)
#define P_BT_601_CTRL0 		CBUS_REG_ADDR(BT_601_CTRL0)
#define P_BT_601_CTRL1 		CBUS_REG_ADDR(BT_601_CTRL1)
#define P_BT_601_CTRL2 		CBUS_REG_ADDR(BT_601_CTRL2)
#define P_BT_601_CTRL3 		CBUS_REG_ADDR(BT_601_CTRL3)
#define P_BT_FIELD_LUMA 		CBUS_REG_ADDR(BT_FIELD_LUMA)
#define P_BT_RAW_CTRL 		CBUS_REG_ADDR(BT_RAW_CTRL)
#define P_BT_STATUS 		CBUS_REG_ADDR(BT_STATUS)
#define P_BT_INT_CTRL 		CBUS_REG_ADDR(BT_INT_CTRL)
#define P_BT_ANCI_STATUS 		CBUS_REG_ADDR(BT_ANCI_STATUS)
#define P_BT_VLINE_STATUS 		CBUS_REG_ADDR(BT_VLINE_STATUS)
#define P_BT_AFIFO_PTR 		CBUS_REG_ADDR(BT_AFIFO_PTR)
#define P_BT_JPEGBYTENUM 		CBUS_REG_ADDR(BT_JPEGBYTENUM)
#define P_BT_ERR_CNT 		CBUS_REG_ADDR(BT_ERR_CNT)
#define P_BT_JPEG_STATUS0 		CBUS_REG_ADDR(BT_JPEG_STATUS0)
#define P_BT_JPEG_STATUS1 		CBUS_REG_ADDR(BT_JPEG_STATUS1)
#define P_BT_LCNT_STATUS 		CBUS_REG_ADDR(BT_LCNT_STATUS)
#define P_BT_PCNT_STATUS 		CBUS_REG_ADDR(BT_PCNT_STATUS)
#define P_BT656_ADDR_END 		CBUS_REG_ADDR(BT656_ADDR_END)
#define P_NDMA_CNTL_REG0 		CBUS_REG_ADDR(NDMA_CNTL_REG0)
#define P_NDMA_TABLE_ADD_REG 		CBUS_REG_ADDR(NDMA_TABLE_ADD_REG)
#define P_NDMA_TDES_KEY_LO 		CBUS_REG_ADDR(NDMA_TDES_KEY_LO)
#define P_NDMA_TDES_KEY_HI 		CBUS_REG_ADDR(NDMA_TDES_KEY_HI)
#define P_NDMA_TDES_CONTROL 		CBUS_REG_ADDR(NDMA_TDES_CONTROL)
#define P_NDMA_AES_CONTROL 		CBUS_REG_ADDR(NDMA_AES_CONTROL)
#define P_NDMA_AES_RK_FIFO 		CBUS_REG_ADDR(NDMA_AES_RK_FIFO)
#define P_NDMA_CRC_OUT 		CBUS_REG_ADDR(NDMA_CRC_OUT)
#define P_NDMA_THREAD_REG 		CBUS_REG_ADDR(NDMA_THREAD_REG)
#define P_NDMA_THREAD_TABLE_START0 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START0)
#define P_NDMA_THREAD_TABLE_CURR0 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR0)
#define P_NDMA_THREAD_TABLE_END0 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END0)
#define P_NDMA_THREAD_TABLE_START1 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START1)
#define P_NDMA_THREAD_TABLE_CURR1 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR1)
#define P_NDMA_THREAD_TABLE_END1 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END1)
#define P_NDMA_THREAD_TABLE_START2 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START2)
#define P_NDMA_THREAD_TABLE_CURR2 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR2)
#define P_NDMA_THREAD_TABLE_END2 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END2)
#define P_NDMA_THREAD_TABLE_START3 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START3)
#define P_NDMA_THREAD_TABLE_CURR3 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR3)
#define P_NDMA_THREAD_TABLE_END3 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END3)
#define P_NDMA_CNTL_REG1 		CBUS_REG_ADDR(NDMA_CNTL_REG1)
#define P_STREAM_EVENT_INFO 		CBUS_REG_ADDR(STREAM_EVENT_INFO)
#define P_STREAM_OUTPUT_CONFIG 		CBUS_REG_ADDR(STREAM_OUTPUT_CONFIG)
#define P_C_D_BUS_CONTROL 		CBUS_REG_ADDR(C_D_BUS_CONTROL)
#define P_C_DATA 		CBUS_REG_ADDR(C_DATA)
#define P_STREAM_BUS_CONFIG 		CBUS_REG_ADDR(STREAM_BUS_CONFIG)
#define P_STREAM_DATA_IN_CONFIG 		CBUS_REG_ADDR(STREAM_DATA_IN_CONFIG)
#define P_STREAM_WAIT_IRQ_CONFIG 		CBUS_REG_ADDR(STREAM_WAIT_IRQ_CONFIG)
#define P_STREAM_EVENT_CTL 		CBUS_REG_ADDR(STREAM_EVENT_CTL)
#define P_CMD_ARGUMENT 		CBUS_REG_ADDR(CMD_ARGUMENT)
#define P_CMD_SEND 		CBUS_REG_ADDR(CMD_SEND)
#define P_SDIO_CONFIG 		CBUS_REG_ADDR(SDIO_CONFIG)
#define P_SDIO_STATUS_IRQ 		CBUS_REG_ADDR(SDIO_STATUS_IRQ)
#define P_SDIO_IRQ_CONFIG 		CBUS_REG_ADDR(SDIO_IRQ_CONFIG)
#define P_SDIO_MULT_CONFIG 		CBUS_REG_ADDR(SDIO_MULT_CONFIG)
#define P_SDIO_M_ADDR 		CBUS_REG_ADDR(SDIO_M_ADDR)
#define P_SDIO_EXTENSION 		CBUS_REG_ADDR(SDIO_EXTENSION)
#define P_ASYNC_FIFO_REG0 		CBUS_REG_ADDR(ASYNC_FIFO_REG0)
#define P_ASYNC_FIFO_REG1 		CBUS_REG_ADDR(ASYNC_FIFO_REG1)
#define P_ASYNC_FIFO_REG2 		CBUS_REG_ADDR(ASYNC_FIFO_REG2)
#define P_ASYNC_FIFO_REG3 		CBUS_REG_ADDR(ASYNC_FIFO_REG3)
#define P_ASYNC_FIFO2_REG0 		CBUS_REG_ADDR(ASYNC_FIFO2_REG0)
#define P_ASYNC_FIFO2_REG1 		CBUS_REG_ADDR(ASYNC_FIFO2_REG1)
#define P_ASYNC_FIFO2_REG2 		CBUS_REG_ADDR(ASYNC_FIFO2_REG2)
#define P_ASYNC_FIFO2_REG3 		CBUS_REG_ADDR(ASYNC_FIFO2_REG3)
#define P_SDIO_AHB_CBUS_CTRL 		CBUS_REG_ADDR(SDIO_AHB_CBUS_CTRL)
#define P_SDIO_AHB_CBUS_M_DATA 		CBUS_REG_ADDR(SDIO_AHB_CBUS_M_DATA)
#define P_SPI_FLASH_CMD 		CBUS_REG_ADDR(SPI_FLASH_CMD)
#define P_SPI_FLASH_ADDR 		CBUS_REG_ADDR(SPI_FLASH_ADDR)
#define P_SPI_FLASH_CTRL 		CBUS_REG_ADDR(SPI_FLASH_CTRL)
#define P_SPI_FLASH_CTRL1 		CBUS_REG_ADDR(SPI_FLASH_CTRL1)
#define P_SPI_FLASH_STATUS 		CBUS_REG_ADDR(SPI_FLASH_STATUS)
#define P_SPI_FLASH_CTRL2 		CBUS_REG_ADDR(SPI_FLASH_CTRL2)
#define P_SPI_FLASH_CLOCK 		CBUS_REG_ADDR(SPI_FLASH_CLOCK)
#define P_SPI_FLASH_USER 		CBUS_REG_ADDR(SPI_FLASH_USER)
#define P_SPI_FLASH_USER1 		CBUS_REG_ADDR(SPI_FLASH_USER1)
#define P_SPI_FLASH_USER2 		CBUS_REG_ADDR(SPI_FLASH_USER2)
#define P_SPI_FLASH_USER3 		CBUS_REG_ADDR(SPI_FLASH_USER3)
#define P_SPI_FLASH_USER4 		CBUS_REG_ADDR(SPI_FLASH_USER4)
#define P_SPI_FLASH_SLAVE 		CBUS_REG_ADDR(SPI_FLASH_SLAVE)
#define P_SPI_FLASH_SLAVE1 		CBUS_REG_ADDR(SPI_FLASH_SLAVE1)
#define P_SPI_FLASH_SLAVE2 		CBUS_REG_ADDR(SPI_FLASH_SLAVE2)
#define P_SPI_FLASH_SLAVE3 		CBUS_REG_ADDR(SPI_FLASH_SLAVE3)
#define P_SPI_FLASH_C0 		CBUS_REG_ADDR(SPI_FLASH_C0)
#define P_SPI_FLASH_C1 		CBUS_REG_ADDR(SPI_FLASH_C1)
#define P_SPI_FLASH_C2 		CBUS_REG_ADDR(SPI_FLASH_C2)
#define P_SPI_FLASH_C3 		CBUS_REG_ADDR(SPI_FLASH_C3)
#define P_SPI_FLASH_C4 		CBUS_REG_ADDR(SPI_FLASH_C4)
#define P_SPI_FLASH_C5 		CBUS_REG_ADDR(SPI_FLASH_C5)
#define P_SPI_FLASH_C6 		CBUS_REG_ADDR(SPI_FLASH_C6)
#define P_SPI_FLASH_C7 		CBUS_REG_ADDR(SPI_FLASH_C7)
#define P_SPI_FLASH_B8 		CBUS_REG_ADDR(SPI_FLASH_B8)
#define P_SPI_FLASH_B9 		CBUS_REG_ADDR(SPI_FLASH_B9)
#define P_SPI_FLASH_B10 		CBUS_REG_ADDR(SPI_FLASH_B10)
#define P_SPI_FLASH_B11 		CBUS_REG_ADDR(SPI_FLASH_B11)
#define P_SPI_FLASH_B12 		CBUS_REG_ADDR(SPI_FLASH_B12)
#define P_SPI_FLASH_B13 		CBUS_REG_ADDR(SPI_FLASH_B13)
#define P_SPI_FLASH_B14 		CBUS_REG_ADDR(SPI_FLASH_B14)
#define P_SPI_FLASH_B15 		CBUS_REG_ADDR(SPI_FLASH_B15)
#define P_SPICC_RXDATA 		CBUS_REG_ADDR(SPICC_RXDATA)
#define P_SPICC_TXDATA 		CBUS_REG_ADDR(SPICC_TXDATA)
#define P_SPICC_CONREG 		CBUS_REG_ADDR(SPICC_CONREG)
#define P_SPICC_INTREG 		CBUS_REG_ADDR(SPICC_INTREG)
#define P_SPICC_DMAREG 		CBUS_REG_ADDR(SPICC_DMAREG)
#define P_SPICC_STATREG 		CBUS_REG_ADDR(SPICC_STATREG)
#define P_SPICC_PERIODREG 		CBUS_REG_ADDR(SPICC_PERIODREG)
#define P_SPICC_TESTREG 		CBUS_REG_ADDR(SPICC_TESTREG)
#define P_SPICC_DRADDR 		CBUS_REG_ADDR(SPICC_DRADDR)
#define P_SPICC_DWADDR 		CBUS_REG_ADDR(SPICC_DWADDR)
#define P_SD_REG0_ARGU 		CBUS_REG_ADDR(SD_REG0_ARGU)
#define P_SD_REG1_SEND 		CBUS_REG_ADDR(SD_REG1_SEND)
#define P_SD_REG2_CNTL 		CBUS_REG_ADDR(SD_REG2_CNTL)
#define P_SD_REG3_STAT 		CBUS_REG_ADDR(SD_REG3_STAT)
#define P_SD_REG4_CLKC 		CBUS_REG_ADDR(SD_REG4_CLKC)
#define P_SD_REG5_ADDR 		CBUS_REG_ADDR(SD_REG5_ADDR)
#define P_SD_REG6_PDMA 		CBUS_REG_ADDR(SD_REG6_PDMA)
#define P_SD_REG7_MISC 		CBUS_REG_ADDR(SD_REG7_MISC)
#define P_SD_REG8_DATA 		CBUS_REG_ADDR(SD_REG8_DATA)
#define P_SD_REG9_ICTL 		CBUS_REG_ADDR(SD_REG9_ICTL)
#define P_SD_REGA_ISTA 		CBUS_REG_ADDR(SD_REGA_ISTA)
#define P_SD_REGB_SRST 		CBUS_REG_ADDR(SD_REGB_SRST)
#define P_ISA_DEBUG_REG0 		CBUS_REG_ADDR(ISA_DEBUG_REG0)
#define P_ISA_DEBUG_REG1 		CBUS_REG_ADDR(ISA_DEBUG_REG1)
#define P_ISA_DEBUG_REG2 		CBUS_REG_ADDR(ISA_DEBUG_REG2)
#define P_ISA_PLL_CLK_SIM0 		CBUS_REG_ADDR(ISA_PLL_CLK_SIM0)
#define P_ISA_CNTL_REG0 		CBUS_REG_ADDR(ISA_CNTL_REG0)
#define P_MEDIA_CPU_IRQ_IN0_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN0_INTR_STAT)
#define P_MEDIA_CPU_IRQ_IN0_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN0_INTR_STAT_CLR)
#define P_MEDIA_CPU_IRQ_IN0_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN0_INTR_MASK)
#define P_MEDIA_CPU_IRQ_IN0_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN0_INTR_FIRQ_SEL)
#define P_MEDIA_CPU_IRQ_IN1_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN1_INTR_STAT)
#define P_MEDIA_CPU_IRQ_IN1_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN1_INTR_STAT_CLR)
#define P_MEDIA_CPU_IRQ_IN1_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN1_INTR_MASK)
#define P_MEDIA_CPU_IRQ_IN1_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN1_INTR_FIRQ_SEL)
#define P_MEDIA_CPU_IRQ_IN2_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN2_INTR_STAT)
#define P_MEDIA_CPU_IRQ_IN2_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN2_INTR_STAT_CLR)
#define P_MEDIA_CPU_IRQ_IN2_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN2_INTR_MASK)
#define P_MEDIA_CPU_IRQ_IN2_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN2_INTR_FIRQ_SEL)
#define P_MEDIA_CPU_IRQ_IN3_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN3_INTR_STAT)
#define P_MEDIA_CPU_IRQ_IN3_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN3_INTR_STAT_CLR)
#define P_MEDIA_CPU_IRQ_IN3_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN3_INTR_MASK)
#define P_MEDIA_CPU_IRQ_IN3_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN3_INTR_FIRQ_SEL)
#define P_GPIO_INTR_EDGE_POL 		CBUS_REG_ADDR(GPIO_INTR_EDGE_POL)
#define P_GPIO_INTR_GPIO_SEL0 		CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL0)
#define P_GPIO_INTR_GPIO_SEL1 		CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL1)
#define P_GPIO_INTR_FILTER_SEL0 		CBUS_REG_ADDR(GPIO_INTR_FILTER_SEL0)
#define P_GLOBAL_INTR_DISABLE 		CBUS_REG_ADDR(GLOBAL_INTR_DISABLE)
#define P_WATCHDOG_TC 		CBUS_REG_ADDR(WATCHDOG_TC)
#define P_WATCHDOG_RESET 		CBUS_REG_ADDR(WATCHDOG_RESET)
#define P_AHB_ARBITER_REG 		CBUS_REG_ADDR(AHB_ARBITER_REG)
#define P_AHB_ARBDEC_REG 		CBUS_REG_ADDR(AHB_ARBDEC_REG)
#define P_AHB_ARBITER2_REG 		CBUS_REG_ADDR(AHB_ARBITER2_REG)
#define P_DEVICE_MMCP_CNTL 		CBUS_REG_ADDR(DEVICE_MMCP_CNTL)
#define P_AUDIO_MMCP_CNTL 		CBUS_REG_ADDR(AUDIO_MMCP_CNTL)
#define P_ISA_BIST_REG0 		CBUS_REG_ADDR(ISA_BIST_REG0)
#define P_ISA_BIST_REG1 		CBUS_REG_ADDR(ISA_BIST_REG1)
#define P_ISA_BIST_REG2 		CBUS_REG_ADDR(ISA_BIST_REG2)
#define P_ISA_BIST_REG3 		CBUS_REG_ADDR(ISA_BIST_REG3)
#define P_ISA_BIST_REG4 		CBUS_REG_ADDR(ISA_BIST_REG4)
#define P_ISA_BIST_REG5 		CBUS_REG_ADDR(ISA_BIST_REG5)
#define P_ISA_BIST_REG6 		CBUS_REG_ADDR(ISA_BIST_REG6)
#define P_ISA_TIMER_MUX 		CBUS_REG_ADDR(ISA_TIMER_MUX)
#define P_ISA_TIMERA 		CBUS_REG_ADDR(ISA_TIMERA)
#define P_ISA_TIMERB 		CBUS_REG_ADDR(ISA_TIMERB)
#define P_ISA_TIMERC 		CBUS_REG_ADDR(ISA_TIMERC)
#define P_ISA_TIMERD 		CBUS_REG_ADDR(ISA_TIMERD)
#define P_ISA_TIMERE 		CBUS_REG_ADDR(ISA_TIMERE)
#define P_FBUF_ADDR 		CBUS_REG_ADDR(FBUF_ADDR)
#define P_SDRAM_CTL0 		CBUS_REG_ADDR(SDRAM_CTL0)
#define P_SDRAM_CTL2 		CBUS_REG_ADDR(SDRAM_CTL2)
#define P_MEDIA_CPU_CTL 		CBUS_REG_ADDR(MEDIA_CPU_CTL)
#define P_SDRAM_CTL4 		CBUS_REG_ADDR(SDRAM_CTL4)
#define P_SDRAM_CTL5 		CBUS_REG_ADDR(SDRAM_CTL5)
#define P_SDRAM_CTL6 		CBUS_REG_ADDR(SDRAM_CTL6)
#define P_SDRAM_CTL7 		CBUS_REG_ADDR(SDRAM_CTL7)
#define P_SDRAM_CTL8 		CBUS_REG_ADDR(SDRAM_CTL8)
#define P_AHB_MP4_MC_CTL 		CBUS_REG_ADDR(AHB_MP4_MC_CTL)
#define P_MEDIA_CPU_PCR 		CBUS_REG_ADDR(MEDIA_CPU_PCR)
#define P_ABUF_WR_CTL0 		CBUS_REG_ADDR(ABUF_WR_CTL0)
#define P_ABUF_WR_CTL1 		CBUS_REG_ADDR(ABUF_WR_CTL1)
#define P_ABUF_WR_CTL2 		CBUS_REG_ADDR(ABUF_WR_CTL2)
#define P_ABUF_WR_CTL3 		CBUS_REG_ADDR(ABUF_WR_CTL3)
#define P_ABUF_RD_CTL0 		CBUS_REG_ADDR(ABUF_RD_CTL0)
#define P_ABUF_RD_CTL1 		CBUS_REG_ADDR(ABUF_RD_CTL1)
#define P_ABUF_RD_CTL2 		CBUS_REG_ADDR(ABUF_RD_CTL2)
#define P_ABUF_RD_CTL3 		CBUS_REG_ADDR(ABUF_RD_CTL3)
#define P_ABUF_ARB_CTL0 		CBUS_REG_ADDR(ABUF_ARB_CTL0)
#define P_ABUF_FIFO_CTL0 		CBUS_REG_ADDR(ABUF_FIFO_CTL0)
#define P_AHB_BRIDGE_CNTL_WR 		CBUS_REG_ADDR(AHB_BRIDGE_CNTL_WR)
#define P_AHB_BRIDGE_REMAP0 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP0)
#define P_AHB_BRIDGE_REMAP1 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP1)
#define P_AHB_BRIDGE_REMAP2 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP2)
#define P_AHB_BRIDGE_REMAP3 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP3)
#define P_AHB_BRIDGE_CNTL_REG1 		CBUS_REG_ADDR(AHB_BRIDGE_CNTL_REG1)
#define P_SYS_CPU_0_IRQ_IN0_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_STAT)
#define P_SYS_CPU_0_IRQ_IN0_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_STAT_CLR)
#define P_SYS_CPU_0_IRQ_IN0_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_MASK)
#define P_SYS_CPU_0_IRQ_IN0_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_FIRQ_SEL)
#define P_SYS_CPU_0_IRQ_IN1_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN1_INTR_STAT)
#define P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR)
#define P_SYS_CPU_0_IRQ_IN1_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN1_INTR_MASK)
#define P_SYS_CPU_0_IRQ_IN1_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN1_INTR_FIRQ_SEL)
#define P_SYS_CPU_0_IRQ_IN2_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN2_INTR_STAT)
#define P_SYS_CPU_0_IRQ_IN2_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN2_INTR_STAT_CLR)
#define P_SYS_CPU_0_IRQ_IN2_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN2_INTR_MASK)
#define P_SYS_CPU_0_IRQ_IN2_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN2_INTR_FIRQ_SEL)
#define P_SYS_CPU_0_IRQ_IN3_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN3_INTR_STAT)
#define P_SYS_CPU_0_IRQ_IN3_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN3_INTR_STAT_CLR)
#define P_SYS_CPU_0_IRQ_IN3_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN3_INTR_MASK)
#define P_SYS_CPU_0_IRQ_IN3_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN3_INTR_FIRQ_SEL)
#define P_SYS_CPU_1_IRQ_IN0_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN0_INTR_STAT)
#define P_SYS_CPU_1_IRQ_IN0_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN0_INTR_STAT_CLR)
#define P_SYS_CPU_1_IRQ_IN0_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN0_INTR_MASK)
#define P_SYS_CPU_1_IRQ_IN0_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN0_INTR_FIRQ_SEL)
#define P_SYS_CPU_1_IRQ_IN1_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN1_INTR_STAT)
#define P_SYS_CPU_1_IRQ_IN1_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN1_INTR_STAT_CLR)
#define P_SYS_CPU_1_IRQ_IN1_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN1_INTR_MASK)
#define P_SYS_CPU_1_IRQ_IN1_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN1_INTR_FIRQ_SEL)
#define P_SYS_CPU_1_IRQ_IN2_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN2_INTR_STAT)
#define P_SYS_CPU_1_IRQ_IN2_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN2_INTR_STAT_CLR)
#define P_SYS_CPU_1_IRQ_IN2_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN2_INTR_MASK)
#define P_SYS_CPU_1_IRQ_IN2_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN2_INTR_FIRQ_SEL)
#define P_SYS_CPU_1_IRQ_IN3_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN3_INTR_STAT)
#define P_SYS_CPU_1_IRQ_IN3_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN3_INTR_STAT_CLR)
#define P_SYS_CPU_1_IRQ_IN3_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN3_INTR_MASK)
#define P_SYS_CPU_1_IRQ_IN3_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN3_INTR_FIRQ_SEL)
#define P_MEDIA_CPU_IRQ_IN4_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN4_INTR_STAT)
#define P_MEDIA_CPU_IRQ_IN4_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN4_INTR_STAT_CLR)
#define P_MEDIA_CPU_IRQ_IN4_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN4_INTR_MASK)
#define P_MEDIA_CPU_IRQ_IN4_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN4_INTR_FIRQ_SEL)
#define P_SYS_CPU_0_IRQ_IN4_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN4_INTR_STAT)
#define P_SYS_CPU_0_IRQ_IN4_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN4_INTR_STAT_CLR)
#define P_SYS_CPU_0_IRQ_IN4_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN4_INTR_MASK)
#define P_SYS_CPU_0_IRQ_IN4_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN4_INTR_FIRQ_SEL)
#define P_SYS_CPU_1_IRQ_IN4_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN4_INTR_STAT)
#define P_SYS_CPU_1_IRQ_IN4_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN4_INTR_STAT_CLR)
#define P_SYS_CPU_1_IRQ_IN4_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN4_INTR_MASK)
#define P_SYS_CPU_1_IRQ_IN4_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN4_INTR_FIRQ_SEL)
#define P_IQ_OM_WIDTH 		CBUS_REG_ADDR(IQ_OM_WIDTH)
#define P_DBG_ADDR_START 		CBUS_REG_ADDR(DBG_ADDR_START)
#define P_DBG_ADDR_END 		CBUS_REG_ADDR(DBG_ADDR_END)
#define P_DBG_CTRL 		CBUS_REG_ADDR(DBG_CTRL)
#define P_DBG_LED 		CBUS_REG_ADDR(DBG_LED)
#define P_DBG_SWITCH 		CBUS_REG_ADDR(DBG_SWITCH)
#define P_DBG_VERSION 		CBUS_REG_ADDR(DBG_VERSION)
#define P_VERSION_CTRL 		CBUS_REG_ADDR(VERSION_CTRL)
#define P_RESET0_REGISTER 		CBUS_REG_ADDR(RESET0_REGISTER)
#define P_RESET1_REGISTER 		CBUS_REG_ADDR(RESET1_REGISTER)
#define P_RESET2_REGISTER 		CBUS_REG_ADDR(RESET2_REGISTER)
#define P_RESET3_REGISTER 		CBUS_REG_ADDR(RESET3_REGISTER)
#define P_RESET4_REGISTER 		CBUS_REG_ADDR(RESET4_REGISTER)
#define P_RESET5_REGISTER 		CBUS_REG_ADDR(RESET5_REGISTER)
#define P_RESET6_REGISTER 		CBUS_REG_ADDR(RESET6_REGISTER)
#define P_RESET0_MASK 		CBUS_REG_ADDR(RESET0_MASK)
#define P_RESET1_MASK 		CBUS_REG_ADDR(RESET1_MASK)
#define P_RESET2_MASK 		CBUS_REG_ADDR(RESET2_MASK)
#define P_RESET3_MASK 		CBUS_REG_ADDR(RESET3_MASK)
#define P_RESET4_MASK 		CBUS_REG_ADDR(RESET4_MASK)
#define P_RESET5_MASK 		CBUS_REG_ADDR(RESET5_MASK)
#define P_RESET6_MASK 		CBUS_REG_ADDR(RESET6_MASK)
#define P_CRT_MASK 		CBUS_REG_ADDR(CRT_MASK)
#define P_SCR_HIU 		CBUS_REG_ADDR(SCR_HIU)
#define P_HPG_TIMER 		CBUS_REG_ADDR(HPG_TIMER)
#define P_HARM_ASB_MB0 		CBUS_REG_ADDR(HARM_ASB_MB0)
#define P_HARM_ASB_MB1 		CBUS_REG_ADDR(HARM_ASB_MB1)
#define P_HARM_ASB_MB2 		CBUS_REG_ADDR(HARM_ASB_MB2)
#define P_HARM_ASB_MB3 		CBUS_REG_ADDR(HARM_ASB_MB3)
#define P_HASB_ARM_MB0 		CBUS_REG_ADDR(HASB_ARM_MB0)
#define P_HASB_ARM_MB1 		CBUS_REG_ADDR(HASB_ARM_MB1)
#define P_HASB_ARM_MB2 		CBUS_REG_ADDR(HASB_ARM_MB2)
#define P_HASB_ARM_MB3 		CBUS_REG_ADDR(HASB_ARM_MB3)
#define P_HHI_TIMER90K 		CBUS_REG_ADDR(HHI_TIMER90K)
#define P_HHI_AUD_DAC_CTRL 		CBUS_REG_ADDR(HHI_AUD_DAC_CTRL)
#define P_HHI_VIID_PLL_CNTL4 		CBUS_REG_ADDR(HHI_VIID_PLL_CNTL4)
#define P_HHI_VIID_PLL_CNTL 		CBUS_REG_ADDR(HHI_VIID_PLL_CNTL)
#define P_HHI_VIID_PLL_CNTL2 		CBUS_REG_ADDR(HHI_VIID_PLL_CNTL2)
#define P_HHI_VIID_PLL_CNTL3 		CBUS_REG_ADDR(HHI_VIID_PLL_CNTL3)
#define P_HHI_VIID_CLK_DIV 		CBUS_REG_ADDR(HHI_VIID_CLK_DIV)
#define P_HHI_VIID_CLK_CNTL 		CBUS_REG_ADDR(HHI_VIID_CLK_CNTL)
#define P_HHI_VIID_DIVIDER_CNTL 		CBUS_REG_ADDR(HHI_VIID_DIVIDER_CNTL)
#define P_HHI_GCLK_MPEG0 		CBUS_REG_ADDR(HHI_GCLK_MPEG0)
#define P_HHI_GCLK_MPEG1 		CBUS_REG_ADDR(HHI_GCLK_MPEG1)
#define P_HHI_GCLK_MPEG2 		CBUS_REG_ADDR(HHI_GCLK_MPEG2)
#define P_HHI_GCLK_OTHER 		CBUS_REG_ADDR(HHI_GCLK_OTHER)
#define P_HHI_GCLK_AO 		CBUS_REG_ADDR(HHI_GCLK_AO)
#define P_HHI_VID_CLK_DIV 		CBUS_REG_ADDR(HHI_VID_CLK_DIV)
#define P_HHI_MPEG_CLK_CNTL 		CBUS_REG_ADDR(HHI_MPEG_CLK_CNTL)
#define P_HHI_AUD_CLK_CNTL 		CBUS_REG_ADDR(HHI_AUD_CLK_CNTL)
#define P_HHI_VID_CLK_CNTL 		CBUS_REG_ADDR(HHI_VID_CLK_CNTL)
#define P_HHI_WIFI_CLK_CNTL 		CBUS_REG_ADDR(HHI_WIFI_CLK_CNTL)
#define P_HHI_WIFI_PLL_CNTL 		CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL)
#define P_HHI_WIFI_PLL_CNTL2 		CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL2)
#define P_HHI_WIFI_PLL_CNTL3 		CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL3)
#define P_HHI_AUD_CLK_CNTL2 		CBUS_REG_ADDR(HHI_AUD_CLK_CNTL2)
#define P_HHI_VID_DIVIDER_CNTL 		CBUS_REG_ADDR(HHI_VID_DIVIDER_CNTL)
#define P_HHI_SYS_CPU_CLK_CNTL 		CBUS_REG_ADDR(HHI_SYS_CPU_CLK_CNTL)
#define P_HHI_DDR_PLL_CNTL 		CBUS_REG_ADDR(HHI_DDR_PLL_CNTL)
#define P_HHI_DDR_PLL_CNTL2 		CBUS_REG_ADDR(HHI_DDR_PLL_CNTL2)
#define P_HHI_DDR_PLL_CNTL3 		CBUS_REG_ADDR(HHI_DDR_PLL_CNTL3)
#define P_HHI_DDR_PLL_CNTL4 		CBUS_REG_ADDR(HHI_DDR_PLL_CNTL4)
#define P_HHI_MALI_CLK_CNTL 		CBUS_REG_ADDR(HHI_MALI_CLK_CNTL)
#define P_HHI_VDEC_CLK_CNTL 		CBUS_REG_ADDR(HHI_VDEC_CLK_CNTL)
#define P_HHI_MIPI_PHY_CLK_CNTL 		CBUS_REG_ADDR(HHI_MIPI_PHY_CLK_CNTL)
#define P_HHI_OTHER_PLL_CNTL 		CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL)
#define P_HHI_OTHER_PLL_CNTL2 		CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL2)
#define P_HHI_OTHER_PLL_CNTL3 		CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL3)
#define P_HHI_HDMI_CLK_CNTL 		CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL)
#define P_HHI_DEMOD_CLK_CNTL 		CBUS_REG_ADDR(HHI_DEMOD_CLK_CNTL)
#define P_HHI_SATA_CLK_CNTL 		CBUS_REG_ADDR(HHI_SATA_CLK_CNTL)
#define P_HHI_ETH_CLK_CNTL 		CBUS_REG_ADDR(HHI_ETH_CLK_CNTL)
#define P_HHI_CLK_DOUBLE_CNTL 		CBUS_REG_ADDR(HHI_CLK_DOUBLE_CNTL)
#define P_HHI_SYS_CPU_AUTO_CLK0 		CBUS_REG_ADDR(HHI_SYS_CPU_AUTO_CLK0)
#define P_HHI_SYS_CPU_AUTO_CLK1 		CBUS_REG_ADDR(HHI_SYS_CPU_AUTO_CLK1)
#define P_HHI_MEDIA_CPU_AUTO_CLK0 		CBUS_REG_ADDR(HHI_MEDIA_CPU_AUTO_CLK0)
#define P_HHI_MEDIA_CPU_AUTO_CLK1 		CBUS_REG_ADDR(HHI_MEDIA_CPU_AUTO_CLK1)
#define P_HHI_HDMI_PLL_CNTL 		CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL)
#define P_HHI_HDMI_PLL_CNTL1 		CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL1)
#define P_HHI_HDMI_PLL_CNTL2 		CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL2)
#define P_HHI_HDMI_AFC_CNTL 		CBUS_REG_ADDR(HHI_HDMI_AFC_CNTL)
#define P_HHI_VID_PLL_MOD_CNTL0 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_CNTL0)
#define P_HHI_VID_PLL_MOD_LOW_TCNT 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_LOW_TCNT)
#define P_HHI_VID_PLL_MOD_HIGH_TCNT 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_HIGH_TCNT)
#define P_HHI_VID_PLL_MOD_NOM_TCNT 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_NOM_TCNT)
#define P_HHI_DDR_CLK_CNTL 		CBUS_REG_ADDR(HHI_DDR_CLK_CNTL)
#define P_HHI_GEN_CLK_CNTL 		CBUS_REG_ADDR(HHI_GEN_CLK_CNTL)
#define P_HHI_GEN_CLK_CNTL2 		CBUS_REG_ADDR(HHI_GEN_CLK_CNTL2)
#define P_HHI_JTAG_CONFIG 		CBUS_REG_ADDR(HHI_JTAG_CONFIG)
#define P_HHI_VAFE_CLKXTALIN_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKXTALIN_CNTL)
#define P_HHI_VAFE_CLKOSCIN_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKOSCIN_CNTL)
#define P_HHI_VAFE_CLKIN_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKIN_CNTL)
#define P_HHI_TVFE_AUTOMODE_CLK_CNTL 		CBUS_REG_ADDR(HHI_TVFE_AUTOMODE_CLK_CNTL)
#define P_HHI_VAFE_CLKPI_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKPI_CNTL)
#define P_HHI_VDIN_MEAS_CLK_CNTL 		CBUS_REG_ADDR(HHI_VDIN_MEAS_CLK_CNTL)
#define P_HHI_PCM_CLK_CNTL 		CBUS_REG_ADDR(HHI_PCM_CLK_CNTL)
#define P_HHI_SYS_PLL_CNTL 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL)
#define P_HHI_SYS_PLL_CNTL2 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL2)
#define P_HHI_SYS_PLL_CNTL3 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL3)
#define P_HHI_SYS_PLL_CNTL4 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL4)
#define P_HHI_VID_PLL_CNTL 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL)
#define P_HHI_VID_PLL_CNTL2 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL2)
#define P_HHI_VID_PLL_CNTL3 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL3)
#define P_HHI_VID_PLL_CNTL4 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL4)
#define P_HHI_MPLL_CNTL 		CBUS_REG_ADDR(HHI_MPLL_CNTL)
#define P_HHI_MPLL_CNTL2 		CBUS_REG_ADDR(HHI_MPLL_CNTL2)
#define P_HHI_MPLL_CNTL3 		CBUS_REG_ADDR(HHI_MPLL_CNTL3)
#define P_HHI_MPLL_CNTL4 		CBUS_REG_ADDR(HHI_MPLL_CNTL4)
#define P_HHI_MPLL_CNTL5 		CBUS_REG_ADDR(HHI_MPLL_CNTL5)
#define P_HHI_MPLL_CNTL6 		CBUS_REG_ADDR(HHI_MPLL_CNTL6)
#define P_HHI_MPLL_CNTL7 		CBUS_REG_ADDR(HHI_MPLL_CNTL7)
#define P_HHI_MPLL_CNTL8 		CBUS_REG_ADDR(HHI_MPLL_CNTL8)
#define P_HHI_MPLL_CNTL9 		CBUS_REG_ADDR(HHI_MPLL_CNTL9)
#define P_HHI_MPLL_CNTL10 		CBUS_REG_ADDR(HHI_MPLL_CNTL10)
#define P_PARSER_CONTROL 		CBUS_REG_ADDR(PARSER_CONTROL)
#define P_PARSER_FETCH_ADDR 		CBUS_REG_ADDR(PARSER_FETCH_ADDR)
#define P_PARSER_FETCH_CMD 		CBUS_REG_ADDR(PARSER_FETCH_CMD)
#define P_PARSER_FETCH_STOP_ADDR 		CBUS_REG_ADDR(PARSER_FETCH_STOP_ADDR)
#define P_PARSER_FETCH_LEVEL 		CBUS_REG_ADDR(PARSER_FETCH_LEVEL)
#define P_PARSER_CONFIG 		CBUS_REG_ADDR(PARSER_CONFIG)
#define P_PFIFO_WR_PTR 		CBUS_REG_ADDR(PFIFO_WR_PTR)
#define P_PFIFO_RD_PTR 		CBUS_REG_ADDR(PFIFO_RD_PTR)
#define P_PFIFO_DATA 		CBUS_REG_ADDR(PFIFO_DATA)
#define P_PARSER_SEARCH_PATTERN 		CBUS_REG_ADDR(PARSER_SEARCH_PATTERN)
#define P_PARSER_SEARCH_MASK 		CBUS_REG_ADDR(PARSER_SEARCH_MASK)
#define P_PARSER_INT_ENABLE 		CBUS_REG_ADDR(PARSER_INT_ENABLE)
#define P_PARSER_INT_STATUS 		CBUS_REG_ADDR(PARSER_INT_STATUS)
#define P_PARSER_SCR_CTL 		CBUS_REG_ADDR(PARSER_SCR_CTL)
#define P_PARSER_SCR 		CBUS_REG_ADDR(PARSER_SCR)
#define P_PARSER_PARAMETER 		CBUS_REG_ADDR(PARSER_PARAMETER)
#define P_PARSER_INSERT_DATA 		CBUS_REG_ADDR(PARSER_INSERT_DATA)
#define P_VAS_STREAM_ID 		CBUS_REG_ADDR(VAS_STREAM_ID)
#define P_VIDEO_DTS 		CBUS_REG_ADDR(VIDEO_DTS)
#define P_VIDEO_PTS 		CBUS_REG_ADDR(VIDEO_PTS)
#define P_VIDEO_PTS_DTS_WR_PTR 		CBUS_REG_ADDR(VIDEO_PTS_DTS_WR_PTR)
#define P_AUDIO_PTS 		CBUS_REG_ADDR(AUDIO_PTS)
#define P_AUDIO_PTS_WR_PTR 		CBUS_REG_ADDR(AUDIO_PTS_WR_PTR)
#define P_PARSER_ES_CONTROL 		CBUS_REG_ADDR(PARSER_ES_CONTROL)
#define P_PFIFO_MONITOR 		CBUS_REG_ADDR(PFIFO_MONITOR)
#define P_PARSER_VIDEO_START_PTR 		CBUS_REG_ADDR(PARSER_VIDEO_START_PTR)
#define P_PARSER_VIDEO_END_PTR 		CBUS_REG_ADDR(PARSER_VIDEO_END_PTR)
#define P_PARSER_VIDEO_WP 		CBUS_REG_ADDR(PARSER_VIDEO_WP)
#define P_PARSER_VIDEO_RP 		CBUS_REG_ADDR(PARSER_VIDEO_RP)
#define P_PARSER_VIDEO_HOLE 		CBUS_REG_ADDR(PARSER_VIDEO_HOLE)
#define P_PARSER_AUDIO_START_PTR 		CBUS_REG_ADDR(PARSER_AUDIO_START_PTR)
#define P_PARSER_AUDIO_END_PTR 		CBUS_REG_ADDR(PARSER_AUDIO_END_PTR)
#define P_PARSER_AUDIO_WP 		CBUS_REG_ADDR(PARSER_AUDIO_WP)
#define P_PARSER_AUDIO_RP 		CBUS_REG_ADDR(PARSER_AUDIO_RP)
#define P_PARSER_AUDIO_HOLE 		CBUS_REG_ADDR(PARSER_AUDIO_HOLE)
#define P_PARSER_SUB_START_PTR 		CBUS_REG_ADDR(PARSER_SUB_START_PTR)
#define P_PARSER_SUB_END_PTR 		CBUS_REG_ADDR(PARSER_SUB_END_PTR)
#define P_PARSER_SUB_WP 		CBUS_REG_ADDR(PARSER_SUB_WP)
#define P_PARSER_SUB_RP 		CBUS_REG_ADDR(PARSER_SUB_RP)
#define P_PARSER_SUB_HOLE 		CBUS_REG_ADDR(PARSER_SUB_HOLE)
#define P_PARSER_FETCH_INFO 		CBUS_REG_ADDR(PARSER_FETCH_INFO)
#define P_PARSER_STATUS 		CBUS_REG_ADDR(PARSER_STATUS)
#define P_PARSER_AV_WRAP_COUNT 		CBUS_REG_ADDR(PARSER_AV_WRAP_COUNT)
#define P_WRRSP_PARSER 		CBUS_REG_ADDR(WRRSP_PARSER)
#define P_PARSER_VIDEO2_START_PTR 		CBUS_REG_ADDR(PARSER_VIDEO2_START_PTR)
#define P_PARSER_VIDEO2_END_PTR 		CBUS_REG_ADDR(PARSER_VIDEO2_END_PTR)
#define P_PARSER_VIDEO2_WP 		CBUS_REG_ADDR(PARSER_VIDEO2_WP)
#define P_PARSER_VIDEO2_RP 		CBUS_REG_ADDR(PARSER_VIDEO2_RP)
#define P_PARSER_VIDEO2_HOLE 		CBUS_REG_ADDR(PARSER_VIDEO2_HOLE)
#define P_PARSER_AV2_WRAP_COUNT 		CBUS_REG_ADDR(PARSER_AV2_WRAP_COUNT)
#define P_VDIN0_OFFSET 		CBUS_REG_ADDR(VDIN0_OFFSET)
#define P_VDIN1_OFFSET 		CBUS_REG_ADDR(VDIN1_OFFSET)
#define P_VDIN_SCALE_COEF_IDX 		CBUS_REG_ADDR(VDIN_SCALE_COEF_IDX)
#define P_VDIN_SCALE_COEF 		CBUS_REG_ADDR(VDIN_SCALE_COEF)
#define P_VDIN_COM_CTRL0 		CBUS_REG_ADDR(VDIN_COM_CTRL0)
#define P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS 		CBUS_REG_ADDR(VDIN_ACTIVE_MAX_PIX_CNT_STATUS)
#define P_VDIN_LCNT_STATUS 		CBUS_REG_ADDR(VDIN_LCNT_STATUS)
#define P_VDIN_COM_STATUS0 		CBUS_REG_ADDR(VDIN_COM_STATUS0)
#define P_VDIN_COM_STATUS1 		CBUS_REG_ADDR(VDIN_COM_STATUS1)
#define P_VDIN_LCNT_SHADOW_STATUS 		CBUS_REG_ADDR(VDIN_LCNT_SHADOW_STATUS)
#define P_VDIN_ASFIFO_CTRL0 		CBUS_REG_ADDR(VDIN_ASFIFO_CTRL0)
#define P_VDIN_ASFIFO_CTRL1 		CBUS_REG_ADDR(VDIN_ASFIFO_CTRL1)
#define P_VDIN_WIDTHM1I_WIDTHM1O 		CBUS_REG_ADDR(VDIN_WIDTHM1I_WIDTHM1O)
#define P_VDIN_SC_MISC_CTRL 		CBUS_REG_ADDR(VDIN_SC_MISC_CTRL)
#define P_VDIN_HSC_PHASE_STEP 		CBUS_REG_ADDR(VDIN_HSC_PHASE_STEP)
#define P_VDIN_HSC_INI_CTRL 		CBUS_REG_ADDR(VDIN_HSC_INI_CTRL)
#define P_VDIN_COM_STATUS2 		CBUS_REG_ADDR(VDIN_COM_STATUS2)
#define P_VDIN_ASFIFO_CTRL2 		CBUS_REG_ADDR(VDIN_ASFIFO_CTRL2)
#define P_VDIN_MATRIX_CTRL 		CBUS_REG_ADDR(VDIN_MATRIX_CTRL)
#define P_VDIN_MATRIX_COEF00_01 		CBUS_REG_ADDR(VDIN_MATRIX_COEF00_01)
#define P_VDIN_MATRIX_COEF02_10 		CBUS_REG_ADDR(VDIN_MATRIX_COEF02_10)
#define P_VDIN_MATRIX_COEF11_12 		CBUS_REG_ADDR(VDIN_MATRIX_COEF11_12)
#define P_VDIN_MATRIX_COEF20_21 		CBUS_REG_ADDR(VDIN_MATRIX_COEF20_21)
#define P_VDIN_MATRIX_COEF22 		CBUS_REG_ADDR(VDIN_MATRIX_COEF22)
#define P_VDIN_MATRIX_OFFSET0_1 		CBUS_REG_ADDR(VDIN_MATRIX_OFFSET0_1)
#define P_VDIN_MATRIX_OFFSET2 		CBUS_REG_ADDR(VDIN_MATRIX_OFFSET2)
#define P_VDIN_MATRIX_PRE_OFFSET0_1 		CBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET0_1)
#define P_VDIN_MATRIX_PRE_OFFSET2 		CBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET2)
#define P_VDIN_LFIFO_CTRL 		CBUS_REG_ADDR(VDIN_LFIFO_CTRL)
#define P_VDIN_COM_GCLK_CTRL 		CBUS_REG_ADDR(VDIN_COM_GCLK_CTRL)
#define P_VDIN_INTF_WIDTHM1 		CBUS_REG_ADDR(VDIN_INTF_WIDTHM1)
#define P_VDIN_WR_CTRL2 		CBUS_REG_ADDR(VDIN_WR_CTRL2)
#define P_VDIN_WR_CTRL 		CBUS_REG_ADDR(VDIN_WR_CTRL)
#define P_VDIN_WR_H_START_END 		CBUS_REG_ADDR(VDIN_WR_H_START_END)
#define P_VDIN_WR_V_START_END 		CBUS_REG_ADDR(VDIN_WR_V_START_END)
#define P_VDIN_HIST_CTRL 		CBUS_REG_ADDR(VDIN_HIST_CTRL)
#define P_VDIN_HIST_H_START_END 		CBUS_REG_ADDR(VDIN_HIST_H_START_END)
#define P_VDIN_HIST_V_START_END 		CBUS_REG_ADDR(VDIN_HIST_V_START_END)
#define P_VDIN_HIST_MAX_MIN 		CBUS_REG_ADDR(VDIN_HIST_MAX_MIN)
#define P_VDIN_HIST_SPL_VAL 		CBUS_REG_ADDR(VDIN_HIST_SPL_VAL)
#define P_VDIN_HIST_SPL_PIX_CNT 		CBUS_REG_ADDR(VDIN_HIST_SPL_PIX_CNT)
#define P_VDIN_HIST_CHROMA_SUM 		CBUS_REG_ADDR(VDIN_HIST_CHROMA_SUM)
#define P_VDIN_DNLP_HIST00 		CBUS_REG_ADDR(VDIN_DNLP_HIST00)
#define P_VDIN_DNLP_HIST01 		CBUS_REG_ADDR(VDIN_DNLP_HIST01)
#define P_VDIN_DNLP_HIST02 		CBUS_REG_ADDR(VDIN_DNLP_HIST02)
#define P_VDIN_DNLP_HIST03 		CBUS_REG_ADDR(VDIN_DNLP_HIST03)
#define P_VDIN_DNLP_HIST04 		CBUS_REG_ADDR(VDIN_DNLP_HIST04)
#define P_VDIN_DNLP_HIST05 		CBUS_REG_ADDR(VDIN_DNLP_HIST05)
#define P_VDIN_DNLP_HIST06 		CBUS_REG_ADDR(VDIN_DNLP_HIST06)
#define P_VDIN_DNLP_HIST07 		CBUS_REG_ADDR(VDIN_DNLP_HIST07)
#define P_VDIN_DNLP_HIST08 		CBUS_REG_ADDR(VDIN_DNLP_HIST08)
#define P_VDIN_DNLP_HIST09 		CBUS_REG_ADDR(VDIN_DNLP_HIST09)
#define P_VDIN_DNLP_HIST10 		CBUS_REG_ADDR(VDIN_DNLP_HIST10)
#define P_VDIN_DNLP_HIST11 		CBUS_REG_ADDR(VDIN_DNLP_HIST11)
#define P_VDIN_DNLP_HIST12 		CBUS_REG_ADDR(VDIN_DNLP_HIST12)
#define P_VDIN_DNLP_HIST13 		CBUS_REG_ADDR(VDIN_DNLP_HIST13)
#define P_VDIN_DNLP_HIST14 		CBUS_REG_ADDR(VDIN_DNLP_HIST14)
#define P_VDIN_DNLP_HIST15 		CBUS_REG_ADDR(VDIN_DNLP_HIST15)
#define P_VDIN_DNLP_HIST16 		CBUS_REG_ADDR(VDIN_DNLP_HIST16)
#define P_VDIN_DNLP_HIST17 		CBUS_REG_ADDR(VDIN_DNLP_HIST17)
#define P_VDIN_DNLP_HIST18 		CBUS_REG_ADDR(VDIN_DNLP_HIST18)
#define P_VDIN_DNLP_HIST19 		CBUS_REG_ADDR(VDIN_DNLP_HIST19)
#define P_VDIN_DNLP_HIST20 		CBUS_REG_ADDR(VDIN_DNLP_HIST20)
#define P_VDIN_DNLP_HIST21 		CBUS_REG_ADDR(VDIN_DNLP_HIST21)
#define P_VDIN_DNLP_HIST22 		CBUS_REG_ADDR(VDIN_DNLP_HIST22)
#define P_VDIN_DNLP_HIST23 		CBUS_REG_ADDR(VDIN_DNLP_HIST23)
#define P_VDIN_DNLP_HIST24 		CBUS_REG_ADDR(VDIN_DNLP_HIST24)
#define P_VDIN_DNLP_HIST25 		CBUS_REG_ADDR(VDIN_DNLP_HIST25)
#define P_VDIN_DNLP_HIST26 		CBUS_REG_ADDR(VDIN_DNLP_HIST26)
#define P_VDIN_DNLP_HIST27 		CBUS_REG_ADDR(VDIN_DNLP_HIST27)
#define P_VDIN_DNLP_HIST28 		CBUS_REG_ADDR(VDIN_DNLP_HIST28)
#define P_VDIN_DNLP_HIST29 		CBUS_REG_ADDR(VDIN_DNLP_HIST29)
#define P_VDIN_DNLP_HIST30 		CBUS_REG_ADDR(VDIN_DNLP_HIST30)
#define P_VDIN_DNLP_HIST31 		CBUS_REG_ADDR(VDIN_DNLP_HIST31)
#define P_VDIN_MEAS_CTRL0 		CBUS_REG_ADDR(VDIN_MEAS_CTRL0)
#define P_VDIN_MEAS_VS_COUNT_HI 		CBUS_REG_ADDR(VDIN_MEAS_VS_COUNT_HI)
#define P_VDIN_MEAS_VS_COUNT_LO 		CBUS_REG_ADDR(VDIN_MEAS_VS_COUNT_LO)
#define P_VDIN_MEAS_HS_RANGE 		CBUS_REG_ADDR(VDIN_MEAS_HS_RANGE)
#define P_VDIN_MEAS_HS_COUNT 		CBUS_REG_ADDR(VDIN_MEAS_HS_COUNT)
#define P_VDIN_BLKBAR_CTRL1 		CBUS_REG_ADDR(VDIN_BLKBAR_CTRL1)
#define P_VDIN_BLKBAR_CTRL0 		CBUS_REG_ADDR(VDIN_BLKBAR_CTRL0)
#define P_VDIN_BLKBAR_H_START_END 		CBUS_REG_ADDR(VDIN_BLKBAR_H_START_END)
#define P_VDIN_BLKBAR_V_START_END 		CBUS_REG_ADDR(VDIN_BLKBAR_V_START_END)
#define P_VDIN_BLKBAR_CNT_THRESHOLD 		CBUS_REG_ADDR(VDIN_BLKBAR_CNT_THRESHOLD)
#define P_VDIN_BLKBAR_ROW_TH1_TH2 		CBUS_REG_ADDR(VDIN_BLKBAR_ROW_TH1_TH2)
#define P_VDIN_BLKBAR_IND_LEFT_START_END 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT_START_END)
#define P_VDIN_BLKBAR_IND_RIGHT_START_END 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT_START_END)
#define P_VDIN_BLKBAR_IND_LEFT1_CNT 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT1_CNT)
#define P_VDIN_BLKBAR_IND_LEFT2_CNT 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT2_CNT)
#define P_VDIN_BLKBAR_IND_RIGHT1_CNT 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT1_CNT)
#define P_VDIN_BLKBAR_IND_RIGHT2_CNT 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT2_CNT)
#define P_VDIN_BLKBAR_STATUS0 		CBUS_REG_ADDR(VDIN_BLKBAR_STATUS0)
#define P_VDIN_BLKBAR_STATUS1 		CBUS_REG_ADDR(VDIN_BLKBAR_STATUS1)
#define P_VDIN_WIN_H_START_END 		CBUS_REG_ADDR(VDIN_WIN_H_START_END)
#define P_VDIN_WIN_V_START_END 		CBUS_REG_ADDR(VDIN_WIN_V_START_END)
#define P_VDIN_ASFIFO_CTRL3 		CBUS_REG_ADDR(VDIN_ASFIFO_CTRL3)
#define P_DVIN_FRONT_END_CTRL 		CBUS_REG_ADDR(DVIN_FRONT_END_CTRL)
#define P_DVIN_HS_LEAD_VS_ODD 		CBUS_REG_ADDR(DVIN_HS_LEAD_VS_ODD)
#define P_DVIN_ACTIVE_START_PIX 		CBUS_REG_ADDR(DVIN_ACTIVE_START_PIX)
#define P_DVIN_ACTIVE_START_LINE 		CBUS_REG_ADDR(DVIN_ACTIVE_START_LINE)
#define P_DVIN_DISPLAY_SIZE 		CBUS_REG_ADDR(DVIN_DISPLAY_SIZE)
#define P_DVIN_CTRL_STAT 		CBUS_REG_ADDR(DVIN_CTRL_STAT)
#define P_VDEC_ASSIST_MMC_CTRL0 		CBUS_REG_ADDR(VDEC_ASSIST_MMC_CTRL0)
#define P_VDEC_ASSIST_MMC_CTRL1 		CBUS_REG_ADDR(VDEC_ASSIST_MMC_CTRL1)
#define P_VDEC_ASSIST_AMR1_INT0 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT0)
#define P_VDEC_ASSIST_AMR1_INT1 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT1)
#define P_VDEC_ASSIST_AMR1_INT2 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT2)
#define P_VDEC_ASSIST_AMR1_INT3 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT3)
#define P_VDEC_ASSIST_AMR1_INT4 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT4)
#define P_VDEC_ASSIST_AMR1_INT5 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT5)
#define P_VDEC_ASSIST_AMR1_INT6 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT6)
#define P_VDEC_ASSIST_AMR1_INT7 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT7)
#define P_VDEC_ASSIST_AMR1_INT8 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT8)
#define P_VDEC_ASSIST_AMR1_INT9 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INT9)
#define P_VDEC_ASSIST_AMR1_INTA 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INTA)
#define P_VDEC_ASSIST_AMR1_INTB 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INTB)
#define P_VDEC_ASSIST_AMR1_INTC 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INTC)
#define P_VDEC_ASSIST_AMR1_INTD 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INTD)
#define P_VDEC_ASSIST_AMR1_INTE 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INTE)
#define P_VDEC_ASSIST_AMR1_INTF 		CBUS_REG_ADDR(VDEC_ASSIST_AMR1_INTF)
#define P_VDEC_ASSIST_AMR2_INT0 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT0)
#define P_VDEC_ASSIST_AMR2_INT1 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT1)
#define P_VDEC_ASSIST_AMR2_INT2 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT2)
#define P_VDEC_ASSIST_AMR2_INT3 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT3)
#define P_VDEC_ASSIST_AMR2_INT4 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT4)
#define P_VDEC_ASSIST_AMR2_INT5 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT5)
#define P_VDEC_ASSIST_AMR2_INT6 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT6)
#define P_VDEC_ASSIST_AMR2_INT7 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT7)
#define P_VDEC_ASSIST_AMR2_INT8 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT8)
#define P_VDEC_ASSIST_AMR2_INT9 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INT9)
#define P_VDEC_ASSIST_AMR2_INTA 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INTA)
#define P_VDEC_ASSIST_AMR2_INTB 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INTB)
#define P_VDEC_ASSIST_AMR2_INTC 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INTC)
#define P_VDEC_ASSIST_AMR2_INTD 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INTD)
#define P_VDEC_ASSIST_AMR2_INTE 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INTE)
#define P_VDEC_ASSIST_AMR2_INTF 		CBUS_REG_ADDR(VDEC_ASSIST_AMR2_INTF)
#define P_VDEC_ASSIST_TIMER0_LO 		CBUS_REG_ADDR(VDEC_ASSIST_TIMER0_LO)
#define P_VDEC_ASSIST_TIMER0_HI 		CBUS_REG_ADDR(VDEC_ASSIST_TIMER0_HI)
#define P_VDEC_ASSIST_TIMER1_LO 		CBUS_REG_ADDR(VDEC_ASSIST_TIMER1_LO)
#define P_VDEC_ASSIST_TIMER1_HI 		CBUS_REG_ADDR(VDEC_ASSIST_TIMER1_HI)
#define P_VDEC_ASSIST_DMA_INT 		CBUS_REG_ADDR(VDEC_ASSIST_DMA_INT)
#define P_VDEC_ASSIST_DMA_INT_MSK 		CBUS_REG_ADDR(VDEC_ASSIST_DMA_INT_MSK)
#define P_VDEC_ASSIST_DMA_INT2 		CBUS_REG_ADDR(VDEC_ASSIST_DMA_INT2)
#define P_VDEC_ASSIST_DMA_INT_MSK2 		CBUS_REG_ADDR(VDEC_ASSIST_DMA_INT_MSK2)
#define P_VDEC_ASSIST_MBOX0_IRQ_REG 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX0_IRQ_REG)
#define P_VDEC_ASSIST_MBOX0_CLR_REG 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX0_CLR_REG)
#define P_VDEC_ASSIST_MBOX0_MASK 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX0_MASK)
#define P_VDEC_ASSIST_MBOX0_FIQ_SEL 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX0_FIQ_SEL)
#define P_VDEC_ASSIST_MBOX1_IRQ_REG 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX1_IRQ_REG)
#define P_VDEC_ASSIST_MBOX1_CLR_REG 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX1_CLR_REG)
#define P_VDEC_ASSIST_MBOX1_MASK 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX1_MASK)
#define P_VDEC_ASSIST_MBOX1_FIQ_SEL 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX1_FIQ_SEL)
#define P_VDEC_ASSIST_MBOX2_IRQ_REG 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX2_IRQ_REG)
#define P_VDEC_ASSIST_MBOX2_CLR_REG 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX2_CLR_REG)
#define P_VDEC_ASSIST_MBOX2_MASK 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX2_MASK)
#define P_VDEC_ASSIST_MBOX2_FIQ_SEL 		CBUS_REG_ADDR(VDEC_ASSIST_MBOX2_FIQ_SEL)
#define P_MC_CTRL_REG 		DOS_REG_ADDR(MC_CTRL_REG)
#define P_MC_MB_INFO 		DOS_REG_ADDR(MC_MB_INFO)
#define P_MC_PIC_INFO 		DOS_REG_ADDR(MC_PIC_INFO)
#define P_MC_HALF_PEL_ONE 		DOS_REG_ADDR(MC_HALF_PEL_ONE)
#define P_MC_HALF_PEL_TWO 		DOS_REG_ADDR(MC_HALF_PEL_TWO)
#define P_POWER_CTL_MC 		DOS_REG_ADDR(POWER_CTL_MC)
#define P_MC_CMD 		DOS_REG_ADDR(MC_CMD)
#define P_MC_CTRL0 		DOS_REG_ADDR(MC_CTRL0)
#define P_MC_PIC_W_H 		DOS_REG_ADDR(MC_PIC_W_H)
#define P_MC_STATUS0 		DOS_REG_ADDR(MC_STATUS0)
#define P_MC_STATUS1 		DOS_REG_ADDR(MC_STATUS1)
#define P_MC_CTRL1 		DOS_REG_ADDR(MC_CTRL1)
#define P_MC_MIX_RATIO0 		DOS_REG_ADDR(MC_MIX_RATIO0)
#define P_MC_MIX_RATIO1 		DOS_REG_ADDR(MC_MIX_RATIO1)
#define P_MC_DP_MB_XY 		DOS_REG_ADDR(MC_DP_MB_XY)
#define P_MC_OM_MB_XY 		DOS_REG_ADDR(MC_OM_MB_XY)
#define P_PSCALE_RST 		DOS_REG_ADDR(PSCALE_RST)
#define P_PSCALE_CTRL 		DOS_REG_ADDR(PSCALE_CTRL)
#define P_PSCALE_PICI_W 		DOS_REG_ADDR(PSCALE_PICI_W)
#define P_PSCALE_PICI_H 		DOS_REG_ADDR(PSCALE_PICI_H)
#define P_PSCALE_PICO_W 		DOS_REG_ADDR(PSCALE_PICO_W)
#define P_PSCALE_PICO_H 		DOS_REG_ADDR(PSCALE_PICO_H)
#define P_PSCALE_PICO_START_X 		DOS_REG_ADDR(PSCALE_PICO_START_X)
#define P_PSCALE_PICO_START_Y 		DOS_REG_ADDR(PSCALE_PICO_START_Y)
#define P_PSCALE_DUMMY 		DOS_REG_ADDR(PSCALE_DUMMY)
#define P_PSCALE_FILT0_COEF0 		DOS_REG_ADDR(PSCALE_FILT0_COEF0)
#define P_PSCALE_FILT0_COEF1 		DOS_REG_ADDR(PSCALE_FILT0_COEF1)
#define P_PSCALE_CMD_CTRL 		DOS_REG_ADDR(PSCALE_CMD_CTRL)
#define P_PSCALE_CMD_BLK_X 		DOS_REG_ADDR(PSCALE_CMD_BLK_X)
#define P_PSCALE_CMD_BLK_Y 		DOS_REG_ADDR(PSCALE_CMD_BLK_Y)
#define P_PSCALE_STATUS 		DOS_REG_ADDR(PSCALE_STATUS)
#define P_PSCALE_BMEM_ADDR 		DOS_REG_ADDR(PSCALE_BMEM_ADDR)
#define P_PSCALE_BMEM_DAT 		DOS_REG_ADDR(PSCALE_BMEM_DAT)
#define P_PSCALE_DRAM_BUF_CTRL 		DOS_REG_ADDR(PSCALE_DRAM_BUF_CTRL)
#define P_PSCALE_MCMD_CTRL 		DOS_REG_ADDR(PSCALE_MCMD_CTRL)
#define P_PSCALE_MCMD_XSIZE 		DOS_REG_ADDR(PSCALE_MCMD_XSIZE)
#define P_PSCALE_MCMD_YSIZE 		DOS_REG_ADDR(PSCALE_MCMD_YSIZE)
#define P_PSCALE_RBUF_START_BLKX 		DOS_REG_ADDR(PSCALE_RBUF_START_BLKX)
#define P_PSCALE_RBUF_START_BLKY 		DOS_REG_ADDR(PSCALE_RBUF_START_BLKY)
#define P_PSCALE_PICO_SHIFT_XY 		DOS_REG_ADDR(PSCALE_PICO_SHIFT_XY)
#define P_PSCALE_CTRL1 		DOS_REG_ADDR(PSCALE_CTRL1)
#define P_PSCALE_SRCKEY_CTRL0 		DOS_REG_ADDR(PSCALE_SRCKEY_CTRL0)
#define P_PSCALE_SRCKEY_CTRL1 		DOS_REG_ADDR(PSCALE_SRCKEY_CTRL1)
#define P_PSCALE_CANVAS_RD_ADDR 		DOS_REG_ADDR(PSCALE_CANVAS_RD_ADDR)
#define P_PSCALE_CANVAS_WR_ADDR 		DOS_REG_ADDR(PSCALE_CANVAS_WR_ADDR)
#define P_PSCALE_CTRL2 		DOS_REG_ADDR(PSCALE_CTRL2)
#define P_MC_MPORT_CTRL 		DOS_REG_ADDR(MC_MPORT_CTRL)
#define P_MC_MPORT_DAT 		DOS_REG_ADDR(MC_MPORT_DAT)
#define P_MC_WT_PRED_CTRL 		DOS_REG_ADDR(MC_WT_PRED_CTRL)
#define P_MC_MBBOT_ST_EVEN_ADDR 		DOS_REG_ADDR(MC_MBBOT_ST_EVEN_ADDR)
#define P_MC_MBBOT_ST_ODD_ADDR 		DOS_REG_ADDR(MC_MBBOT_ST_ODD_ADDR)
#define P_MC_DPDN_MB_XY 		DOS_REG_ADDR(MC_DPDN_MB_XY)
#define P_MC_OMDN_MB_XY 		DOS_REG_ADDR(MC_OMDN_MB_XY)
#define P_MC_HCMDBUF_H 		DOS_REG_ADDR(MC_HCMDBUF_H)
#define P_MC_HCMDBUF_L 		DOS_REG_ADDR(MC_HCMDBUF_L)
#define P_MC_HCMD_H 		DOS_REG_ADDR(MC_HCMD_H)
#define P_MC_HCMD_L 		DOS_REG_ADDR(MC_HCMD_L)
#define P_MC_IDCT_DAT 		DOS_REG_ADDR(MC_IDCT_DAT)
#define P_MC_CTRL_GCLK_CTRL 		DOS_REG_ADDR(MC_CTRL_GCLK_CTRL)
#define P_MC_OTHER_GCLK_CTRL 		DOS_REG_ADDR(MC_OTHER_GCLK_CTRL)
#define P_MC_CTRL2 		DOS_REG_ADDR(MC_CTRL2)
#define P_MDEC_PIC_DC_CTRL 		DOS_REG_ADDR(MDEC_PIC_DC_CTRL)
#define P_MDEC_PIC_DC_STATUS 		DOS_REG_ADDR(MDEC_PIC_DC_STATUS)
#define P_ANC0_CANVAS_ADDR 		DOS_REG_ADDR(ANC0_CANVAS_ADDR)
#define P_ANC1_CANVAS_ADDR 		DOS_REG_ADDR(ANC1_CANVAS_ADDR)
#define P_ANC2_CANVAS_ADDR 		DOS_REG_ADDR(ANC2_CANVAS_ADDR)
#define P_ANC3_CANVAS_ADDR 		DOS_REG_ADDR(ANC3_CANVAS_ADDR)
#define P_ANC4_CANVAS_ADDR 		DOS_REG_ADDR(ANC4_CANVAS_ADDR)
#define P_ANC5_CANVAS_ADDR 		DOS_REG_ADDR(ANC5_CANVAS_ADDR)
#define P_ANC6_CANVAS_ADDR 		DOS_REG_ADDR(ANC6_CANVAS_ADDR)
#define P_ANC7_CANVAS_ADDR 		DOS_REG_ADDR(ANC7_CANVAS_ADDR)
#define P_ANC8_CANVAS_ADDR 		DOS_REG_ADDR(ANC8_CANVAS_ADDR)
#define P_ANC9_CANVAS_ADDR 		DOS_REG_ADDR(ANC9_CANVAS_ADDR)
#define P_ANC10_CANVAS_ADDR 		DOS_REG_ADDR(ANC10_CANVAS_ADDR)
#define P_ANC11_CANVAS_ADDR 		DOS_REG_ADDR(ANC11_CANVAS_ADDR)
#define P_ANC12_CANVAS_ADDR 		DOS_REG_ADDR(ANC12_CANVAS_ADDR)
#define P_ANC13_CANVAS_ADDR 		DOS_REG_ADDR(ANC13_CANVAS_ADDR)
#define P_ANC14_CANVAS_ADDR 		DOS_REG_ADDR(ANC14_CANVAS_ADDR)
#define P_ANC15_CANVAS_ADDR 		DOS_REG_ADDR(ANC15_CANVAS_ADDR)
#define P_ANC16_CANVAS_ADDR 		DOS_REG_ADDR(ANC16_CANVAS_ADDR)
#define P_ANC17_CANVAS_ADDR 		DOS_REG_ADDR(ANC17_CANVAS_ADDR)
#define P_ANC18_CANVAS_ADDR 		DOS_REG_ADDR(ANC18_CANVAS_ADDR)
#define P_ANC19_CANVAS_ADDR 		DOS_REG_ADDR(ANC19_CANVAS_ADDR)
#define P_ANC20_CANVAS_ADDR 		DOS_REG_ADDR(ANC20_CANVAS_ADDR)
#define P_ANC21_CANVAS_ADDR 		DOS_REG_ADDR(ANC21_CANVAS_ADDR)
#define P_ANC22_CANVAS_ADDR 		DOS_REG_ADDR(ANC22_CANVAS_ADDR)
#define P_ANC23_CANVAS_ADDR 		DOS_REG_ADDR(ANC23_CANVAS_ADDR)
#define P_ANC24_CANVAS_ADDR 		DOS_REG_ADDR(ANC24_CANVAS_ADDR)
#define P_ANC25_CANVAS_ADDR 		DOS_REG_ADDR(ANC25_CANVAS_ADDR)
#define P_ANC26_CANVAS_ADDR 		DOS_REG_ADDR(ANC26_CANVAS_ADDR)
#define P_ANC27_CANVAS_ADDR 		DOS_REG_ADDR(ANC27_CANVAS_ADDR)
#define P_ANC28_CANVAS_ADDR 		DOS_REG_ADDR(ANC28_CANVAS_ADDR)
#define P_ANC29_CANVAS_ADDR 		DOS_REG_ADDR(ANC29_CANVAS_ADDR)
#define P_ANC30_CANVAS_ADDR 		DOS_REG_ADDR(ANC30_CANVAS_ADDR)
#define P_ANC31_CANVAS_ADDR 		DOS_REG_ADDR(ANC31_CANVAS_ADDR)
#define P_DBKR_CANVAS_ADDR 		DOS_REG_ADDR(DBKR_CANVAS_ADDR)
#define P_DBKW_CANVAS_ADDR 		DOS_REG_ADDR(DBKW_CANVAS_ADDR)
#define P_REC_CANVAS_ADDR 		DOS_REG_ADDR(REC_CANVAS_ADDR)
#define P_CURR_CANVAS_CTRL 		DOS_REG_ADDR(CURR_CANVAS_CTRL)
#define P_MDEC_PIC_DC_THRESH 		DOS_REG_ADDR(MDEC_PIC_DC_THRESH)
#define P_MDEC_PICR_BUF_STATUS 		DOS_REG_ADDR(MDEC_PICR_BUF_STATUS)
#define P_MDEC_PICW_BUF_STATUS 		DOS_REG_ADDR(MDEC_PICW_BUF_STATUS)
#define P_MCW_DBLK_WRRSP_CNT 		DOS_REG_ADDR(MCW_DBLK_WRRSP_CNT)
#define P_AV_SCRATCH_0 		DOS_REG_ADDR(AV_SCRATCH_0)
#define P_AV_SCRATCH_1 		DOS_REG_ADDR(AV_SCRATCH_1)
#define P_AV_SCRATCH_2 		DOS_REG_ADDR(AV_SCRATCH_2)
#define P_AV_SCRATCH_3 		DOS_REG_ADDR(AV_SCRATCH_3)
#define P_AV_SCRATCH_4 		DOS_REG_ADDR(AV_SCRATCH_4)
#define P_AV_SCRATCH_5 		DOS_REG_ADDR(AV_SCRATCH_5)
#define P_AV_SCRATCH_6 		DOS_REG_ADDR(AV_SCRATCH_6)
#define P_AV_SCRATCH_7 		DOS_REG_ADDR(AV_SCRATCH_7)
#define P_AV_SCRATCH_8 		DOS_REG_ADDR(AV_SCRATCH_8)
#define P_AV_SCRATCH_9 		DOS_REG_ADDR(AV_SCRATCH_9)
#define P_AV_SCRATCH_A 		DOS_REG_ADDR(AV_SCRATCH_A)
#define P_AV_SCRATCH_B 		DOS_REG_ADDR(AV_SCRATCH_B)
#define P_AV_SCRATCH_C 		DOS_REG_ADDR(AV_SCRATCH_C)
#define P_AV_SCRATCH_D 		DOS_REG_ADDR(AV_SCRATCH_D)
#define P_AV_SCRATCH_E 		DOS_REG_ADDR(AV_SCRATCH_E)
#define P_AV_SCRATCH_F 		DOS_REG_ADDR(AV_SCRATCH_F)
#define P_AV_SCRATCH_G 		DOS_REG_ADDR(AV_SCRATCH_G)
#define P_AV_SCRATCH_H 		DOS_REG_ADDR(AV_SCRATCH_H)
#define P_AV_SCRATCH_I 		DOS_REG_ADDR(AV_SCRATCH_I)
#define P_AV_SCRATCH_J 		DOS_REG_ADDR(AV_SCRATCH_J)
#define P_AV_SCRATCH_K 		DOS_REG_ADDR(AV_SCRATCH_K)
#define P_AV_SCRATCH_L 		DOS_REG_ADDR(AV_SCRATCH_L)
#define P_AV_SCRATCH_M 		DOS_REG_ADDR(AV_SCRATCH_M)
#define P_AV_SCRATCH_N 		DOS_REG_ADDR(AV_SCRATCH_N)
#define P_WRRSP_CO_MB 		DOS_REG_ADDR(WRRSP_CO_MB)
#define P_WRRSP_DCAC 		DOS_REG_ADDR(WRRSP_DCAC)
#define P_DBLK_RST 		DOS_REG_ADDR(DBLK_RST)
#define P_DBLK_CTRL 		DOS_REG_ADDR(DBLK_CTRL)
#define P_DBLK_MB_WID_HEIGHT 		DOS_REG_ADDR(DBLK_MB_WID_HEIGHT)
#define P_DBLK_STATUS 		DOS_REG_ADDR(DBLK_STATUS)
#define P_DBLK_CMD_CTRL 		DOS_REG_ADDR(DBLK_CMD_CTRL)
#define P_DBLK_MB_XY 		DOS_REG_ADDR(DBLK_MB_XY)
#define P_DBLK_QP 		DOS_REG_ADDR(DBLK_QP)
#define P_DBLK_Y_BHFILT 		DOS_REG_ADDR(DBLK_Y_BHFILT)
#define P_DBLK_Y_BHFILT_HIGH 		DOS_REG_ADDR(DBLK_Y_BHFILT_HIGH)
#define P_DBLK_Y_BVFILT 		DOS_REG_ADDR(DBLK_Y_BVFILT)
#define P_DBLK_CB_BFILT 		DOS_REG_ADDR(DBLK_CB_BFILT)
#define P_DBLK_CR_BFILT 		DOS_REG_ADDR(DBLK_CR_BFILT)
#define P_DBLK_Y_HFILT 		DOS_REG_ADDR(DBLK_Y_HFILT)
#define P_DBLK_Y_HFILT_HIGH 		DOS_REG_ADDR(DBLK_Y_HFILT_HIGH)
#define P_DBLK_Y_VFILT 		DOS_REG_ADDR(DBLK_Y_VFILT)
#define P_DBLK_CB_FILT 		DOS_REG_ADDR(DBLK_CB_FILT)
#define P_DBLK_CR_FILT 		DOS_REG_ADDR(DBLK_CR_FILT)
#define P_DBLK_BETAX_QP_SEL 		DOS_REG_ADDR(DBLK_BETAX_QP_SEL)
#define P_DBLK_CLIP_CTRL0 		DOS_REG_ADDR(DBLK_CLIP_CTRL0)
#define P_DBLK_CLIP_CTRL1 		DOS_REG_ADDR(DBLK_CLIP_CTRL1)
#define P_DBLK_CLIP_CTRL2 		DOS_REG_ADDR(DBLK_CLIP_CTRL2)
#define P_DBLK_CLIP_CTRL3 		DOS_REG_ADDR(DBLK_CLIP_CTRL3)
#define P_DBLK_CLIP_CTRL4 		DOS_REG_ADDR(DBLK_CLIP_CTRL4)
#define P_DBLK_CLIP_CTRL5 		DOS_REG_ADDR(DBLK_CLIP_CTRL5)
#define P_DBLK_CLIP_CTRL6 		DOS_REG_ADDR(DBLK_CLIP_CTRL6)
#define P_DBLK_CLIP_CTRL7 		DOS_REG_ADDR(DBLK_CLIP_CTRL7)
#define P_DBLK_CLIP_CTRL8 		DOS_REG_ADDR(DBLK_CLIP_CTRL8)
#define P_DBLK_STATUS1 		DOS_REG_ADDR(DBLK_STATUS1)
#define P_DBLK_GCLK_FREE 		DOS_REG_ADDR(DBLK_GCLK_FREE)
#define P_DBLK_GCLK_OFF 		DOS_REG_ADDR(DBLK_GCLK_OFF)
#define P_DBLK_AVSFLAGS 		DOS_REG_ADDR(DBLK_AVSFLAGS)
#define P_DBLK_CBPY 		DOS_REG_ADDR(DBLK_CBPY)
#define P_DBLK_CBPY_ADJ 		DOS_REG_ADDR(DBLK_CBPY_ADJ)
#define P_DBLK_CBPC 		DOS_REG_ADDR(DBLK_CBPC)
#define P_DBLK_CBPC_ADJ 		DOS_REG_ADDR(DBLK_CBPC_ADJ)
#define P_DBLK_VHMVD 		DOS_REG_ADDR(DBLK_VHMVD)
#define P_DBLK_STRONG 		DOS_REG_ADDR(DBLK_STRONG)
#define P_DBLK_RV8_QUANT 		DOS_REG_ADDR(DBLK_RV8_QUANT)
#define P_DBLK_CBUS_HCMD2 		DOS_REG_ADDR(DBLK_CBUS_HCMD2)
#define P_DBLK_CBUS_HCMD1 		DOS_REG_ADDR(DBLK_CBUS_HCMD1)
#define P_DBLK_CBUS_HCMD0 		DOS_REG_ADDR(DBLK_CBUS_HCMD0)
#define P_DBLK_VLD_HCMD2 		DOS_REG_ADDR(DBLK_VLD_HCMD2)
#define P_DBLK_VLD_HCMD1 		DOS_REG_ADDR(DBLK_VLD_HCMD1)
#define P_DBLK_VLD_HCMD0 		DOS_REG_ADDR(DBLK_VLD_HCMD0)
#define P_DBLK_OST_YBASE 		DOS_REG_ADDR(DBLK_OST_YBASE)
#define P_DBLK_OST_CBCRDIFF 		DOS_REG_ADDR(DBLK_OST_CBCRDIFF)
#define P_DBLK_CTRL1 		DOS_REG_ADDR(DBLK_CTRL1)
#define P_VLD_STATUS_CTRL 		DOS_REG_ADDR(VLD_STATUS_CTRL)
#define P_MPEG1_2_REG 		DOS_REG_ADDR(MPEG1_2_REG)
#define P_F_CODE_REG 		DOS_REG_ADDR(F_CODE_REG)
#define P_PIC_HEAD_INFO 		DOS_REG_ADDR(PIC_HEAD_INFO)
#define P_SLICE_VER_POS_PIC_TYPE 		DOS_REG_ADDR(SLICE_VER_POS_PIC_TYPE)
#define P_QP_VALUE_REG 		DOS_REG_ADDR(QP_VALUE_REG)
#define P_MBA_INC 		DOS_REG_ADDR(MBA_INC)
#define P_MB_MOTION_MODE 		DOS_REG_ADDR(MB_MOTION_MODE)
#define P_POWER_CTL_VLD 		DOS_REG_ADDR(POWER_CTL_VLD)
#define P_MB_WIDTH 		DOS_REG_ADDR(MB_WIDTH)
#define P_SLICE_QP 		DOS_REG_ADDR(SLICE_QP)
#define P_PRE_START_CODE 		DOS_REG_ADDR(PRE_START_CODE)
#define P_SLICE_START_BYTE_01 		DOS_REG_ADDR(SLICE_START_BYTE_01)
#define P_SLICE_START_BYTE_23 		DOS_REG_ADDR(SLICE_START_BYTE_23)
#define P_RESYNC_MARKER_LENGTH 		DOS_REG_ADDR(RESYNC_MARKER_LENGTH)
#define P_DECODER_BUFFER_INFO 		DOS_REG_ADDR(DECODER_BUFFER_INFO)
#define P_FST_FOR_MV_X 		DOS_REG_ADDR(FST_FOR_MV_X)
#define P_FST_FOR_MV_Y 		DOS_REG_ADDR(FST_FOR_MV_Y)
#define P_SCD_FOR_MV_X 		DOS_REG_ADDR(SCD_FOR_MV_X)
#define P_SCD_FOR_MV_Y 		DOS_REG_ADDR(SCD_FOR_MV_Y)
#define P_FST_BAK_MV_X 		DOS_REG_ADDR(FST_BAK_MV_X)
#define P_FST_BAK_MV_Y 		DOS_REG_ADDR(FST_BAK_MV_Y)
#define P_SCD_BAK_MV_X 		DOS_REG_ADDR(SCD_BAK_MV_X)
#define P_SCD_BAK_MV_Y 		DOS_REG_ADDR(SCD_BAK_MV_Y)
#define P_VLD_DECODE_CONTROL 		DOS_REG_ADDR(VLD_DECODE_CONTROL)
#define P_VLD_REVERVED_19 		DOS_REG_ADDR(VLD_REVERVED_19)
#define P_VIFF_BIT_CNT 		DOS_REG_ADDR(VIFF_BIT_CNT)
#define P_BYTE_ALIGN_PEAK_HI 		DOS_REG_ADDR(BYTE_ALIGN_PEAK_HI)
#define P_BYTE_ALIGN_PEAK_LO 		DOS_REG_ADDR(BYTE_ALIGN_PEAK_LO)
#define P_NEXT_ALIGN_PEAK 		DOS_REG_ADDR(NEXT_ALIGN_PEAK)
#define P_VC1_CONTROL_REG 		DOS_REG_ADDR(VC1_CONTROL_REG)
#define P_PMV1_X 		DOS_REG_ADDR(PMV1_X)
#define P_PMV1_Y 		DOS_REG_ADDR(PMV1_Y)
#define P_PMV2_X 		DOS_REG_ADDR(PMV2_X)
#define P_PMV2_Y 		DOS_REG_ADDR(PMV2_Y)
#define P_PMV3_X 		DOS_REG_ADDR(PMV3_X)
#define P_PMV3_Y 		DOS_REG_ADDR(PMV3_Y)
#define P_PMV4_X 		DOS_REG_ADDR(PMV4_X)
#define P_PMV4_Y 		DOS_REG_ADDR(PMV4_Y)
#define P_M4_TABLE_SELECT 		DOS_REG_ADDR(M4_TABLE_SELECT)
#define P_M4_CONTROL_REG 		DOS_REG_ADDR(M4_CONTROL_REG)
#define P_BLOCK_NUM 		DOS_REG_ADDR(BLOCK_NUM)
#define P_PATTERN_CODE 		DOS_REG_ADDR(PATTERN_CODE)
#define P_MB_INFO 		DOS_REG_ADDR(MB_INFO)
#define P_VLD_DC_PRED 		DOS_REG_ADDR(VLD_DC_PRED)
#define P_VLD_ERROR_MASK 		DOS_REG_ADDR(VLD_ERROR_MASK)
#define P_VLD_DC_PRED_C 		DOS_REG_ADDR(VLD_DC_PRED_C)
#define P_LAST_SLICE_MV_ADDR 		DOS_REG_ADDR(LAST_SLICE_MV_ADDR)
#define P_LAST_MVX 		DOS_REG_ADDR(LAST_MVX)
#define P_LAST_MVY 		DOS_REG_ADDR(LAST_MVY)
#define P_VLD_C38 		DOS_REG_ADDR(VLD_C38)
#define P_VLD_C39 		DOS_REG_ADDR(VLD_C39)
#define P_VLD_STATUS 		DOS_REG_ADDR(VLD_STATUS)
#define P_VLD_SHIFT_STATUS 		DOS_REG_ADDR(VLD_SHIFT_STATUS)
#define P_VOFF_STATUS 		DOS_REG_ADDR(VOFF_STATUS)
#define P_VLD_C3D 		DOS_REG_ADDR(VLD_C3D)
#define P_VLD_DBG_INDEX 		DOS_REG_ADDR(VLD_DBG_INDEX)
#define P_VLD_DBG_DATA 		DOS_REG_ADDR(VLD_DBG_DATA)
#define P_VLD_MEM_VIFIFO_START_PTR 		DOS_REG_ADDR(VLD_MEM_VIFIFO_START_PTR)
#define P_VLD_MEM_VIFIFO_CURR_PTR 		DOS_REG_ADDR(VLD_MEM_VIFIFO_CURR_PTR)
#define P_VLD_MEM_VIFIFO_END_PTR 		DOS_REG_ADDR(VLD_MEM_VIFIFO_END_PTR)
#define P_VLD_MEM_VIFIFO_BYTES_AVAIL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_BYTES_AVAIL)
#define P_VLD_MEM_VIFIFO_CONTROL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_CONTROL)
#define P_VLD_MEM_VIFIFO_WP 		DOS_REG_ADDR(VLD_MEM_VIFIFO_WP)
#define P_VLD_MEM_VIFIFO_RP 		DOS_REG_ADDR(VLD_MEM_VIFIFO_RP)
#define P_VLD_MEM_VIFIFO_LEVEL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_LEVEL)
#define P_VLD_MEM_VIFIFO_BUF_CNTL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_BUF_CNTL)
#define P_VLD_TIME_STAMP_CNTL 		DOS_REG_ADDR(VLD_TIME_STAMP_CNTL)
#define P_VLD_TIME_STAMP_SYNC_0 		DOS_REG_ADDR(VLD_TIME_STAMP_SYNC_0)
#define P_VLD_TIME_STAMP_SYNC_1 		DOS_REG_ADDR(VLD_TIME_STAMP_SYNC_1)
#define P_VLD_TIME_STAMP_0 		DOS_REG_ADDR(VLD_TIME_STAMP_0)
#define P_VLD_TIME_STAMP_1 		DOS_REG_ADDR(VLD_TIME_STAMP_1)
#define P_VLD_TIME_STAMP_2 		DOS_REG_ADDR(VLD_TIME_STAMP_2)
#define P_VLD_TIME_STAMP_3 		DOS_REG_ADDR(VLD_TIME_STAMP_3)
#define P_VLD_TIME_STAMP_LENGTH 		DOS_REG_ADDR(VLD_TIME_STAMP_LENGTH)
#define P_VLD_MEM_VIFIFO_WRAP_COUNT 		DOS_REG_ADDR(VLD_MEM_VIFIFO_WRAP_COUNT)
#define P_VLD_MEM_VIFIFO_MEM_CTL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_MEM_CTL)
#define P_VLD_MEM_VBUF_RD_PTR 		DOS_REG_ADDR(VLD_MEM_VBUF_RD_PTR)
#define P_VLD_MEM_VBUF2_RD_PTR 		DOS_REG_ADDR(VLD_MEM_VBUF2_RD_PTR)
#define P_VLD_MEM_SWAP_ADDR 		DOS_REG_ADDR(VLD_MEM_SWAP_ADDR)
#define P_VLD_MEM_SWAP_CTL 		DOS_REG_ADDR(VLD_MEM_SWAP_CTL)
#define P_VCOP_CTRL_REG 		DOS_REG_ADDR(VCOP_CTRL_REG)
#define P_QP_CTRL_REG 		DOS_REG_ADDR(QP_CTRL_REG)
#define P_INTRA_QUANT_MATRIX 		DOS_REG_ADDR(INTRA_QUANT_MATRIX)
#define P_NON_I_QUANT_MATRIX 		DOS_REG_ADDR(NON_I_QUANT_MATRIX)
#define P_DC_SCALER 		DOS_REG_ADDR(DC_SCALER)
#define P_DC_AC_CTRL 		DOS_REG_ADDR(DC_AC_CTRL)
#define P_DC_AC_SCALE_MUL 		DOS_REG_ADDR(DC_AC_SCALE_MUL)
#define P_DC_AC_SCALE_DIV 		DOS_REG_ADDR(DC_AC_SCALE_DIV)
#define P_POWER_CTL_IQIDCT 		DOS_REG_ADDR(POWER_CTL_IQIDCT)
#define P_RV_AI_Y_X 		DOS_REG_ADDR(RV_AI_Y_X)
#define P_RV_AI_U_X 		DOS_REG_ADDR(RV_AI_U_X)
#define P_RV_AI_V_X 		DOS_REG_ADDR(RV_AI_V_X)
#define P_RV_AI_MB_COUNT 		DOS_REG_ADDR(RV_AI_MB_COUNT)
#define P_NEXT_INTRA_DMA_ADDRESS 		DOS_REG_ADDR(NEXT_INTRA_DMA_ADDRESS)
#define P_IQIDCT_CONTROL 		DOS_REG_ADDR(IQIDCT_CONTROL)
#define P_IQIDCT_DEBUG_INFO_0 		DOS_REG_ADDR(IQIDCT_DEBUG_INFO_0)
#define P_DEBLK_CMD 		DOS_REG_ADDR(DEBLK_CMD)
#define P_IQIDCT_DEBUG_IDCT 		DOS_REG_ADDR(IQIDCT_DEBUG_IDCT)
#define P_DCAC_DMA_CTRL 		DOS_REG_ADDR(DCAC_DMA_CTRL)
#define P_DCAC_DMA_ADDRESS 		DOS_REG_ADDR(DCAC_DMA_ADDRESS)
#define P_DCAC_CPU_ADDRESS 		DOS_REG_ADDR(DCAC_CPU_ADDRESS)
#define P_DCAC_CPU_DATA 		DOS_REG_ADDR(DCAC_CPU_DATA)
#define P_DCAC_MB_COUNT 		DOS_REG_ADDR(DCAC_MB_COUNT)
#define P_IQ_QUANT 		DOS_REG_ADDR(IQ_QUANT)
#define P_VC1_BITPLANE_CTL 		DOS_REG_ADDR(VC1_BITPLANE_CTL)
#define P_MSP 		DOS_REG_ADDR(MSP)
#define P_MPSR 		DOS_REG_ADDR(MPSR)
#define P_MINT_VEC_BASE 		DOS_REG_ADDR(MINT_VEC_BASE)
#define P_MCPU_INTR_GRP 		DOS_REG_ADDR(MCPU_INTR_GRP)
#define P_MCPU_INTR_MSK 		DOS_REG_ADDR(MCPU_INTR_MSK)
#define P_MCPU_INTR_REQ 		DOS_REG_ADDR(MCPU_INTR_REQ)
#define P_MPC_P 		DOS_REG_ADDR(MPC_P)
#define P_MPC_D 		DOS_REG_ADDR(MPC_D)
#define P_MPC_E 		DOS_REG_ADDR(MPC_E)
#define P_MPC_W 		DOS_REG_ADDR(MPC_W)
#define P_MINDEX0_REG 		DOS_REG_ADDR(MINDEX0_REG)
#define P_MINDEX1_REG 		DOS_REG_ADDR(MINDEX1_REG)
#define P_MINDEX2_REG 		DOS_REG_ADDR(MINDEX2_REG)
#define P_MINDEX3_REG 		DOS_REG_ADDR(MINDEX3_REG)
#define P_MINDEX4_REG 		DOS_REG_ADDR(MINDEX4_REG)
#define P_MINDEX5_REG 		DOS_REG_ADDR(MINDEX5_REG)
#define P_MINDEX6_REG 		DOS_REG_ADDR(MINDEX6_REG)
#define P_MINDEX7_REG 		DOS_REG_ADDR(MINDEX7_REG)
#define P_MMIN_REG 		DOS_REG_ADDR(MMIN_REG)
#define P_MMAX_REG 		DOS_REG_ADDR(MMAX_REG)
#define P_MBREAK0_REG 		DOS_REG_ADDR(MBREAK0_REG)
#define P_MBREAK1_REG 		DOS_REG_ADDR(MBREAK1_REG)
#define P_MBREAK2_REG 		DOS_REG_ADDR(MBREAK2_REG)
#define P_MBREAK3_REG 		DOS_REG_ADDR(MBREAK3_REG)
#define P_MBREAK_TYPE 		DOS_REG_ADDR(MBREAK_TYPE)
#define P_MBREAK_CTRL 		DOS_REG_ADDR(MBREAK_CTRL)
#define P_MBREAK_STAUTS 		DOS_REG_ADDR(MBREAK_STAUTS)
#define P_MDB_ADDR_REG 		DOS_REG_ADDR(MDB_ADDR_REG)
#define P_MDB_DATA_REG 		DOS_REG_ADDR(MDB_DATA_REG)
#define P_MDB_CTRL 		DOS_REG_ADDR(MDB_CTRL)
#define P_MSFTINT0 		DOS_REG_ADDR(MSFTINT0)
#define P_MSFTINT1 		DOS_REG_ADDR(MSFTINT1)
#define P_CSP 		DOS_REG_ADDR(CSP)
#define P_CPSR 		DOS_REG_ADDR(CPSR)
#define P_CINT_VEC_BASE 		DOS_REG_ADDR(CINT_VEC_BASE)
#define P_CCPU_INTR_GRP 		DOS_REG_ADDR(CCPU_INTR_GRP)
#define P_CCPU_INTR_MSK 		DOS_REG_ADDR(CCPU_INTR_MSK)
#define P_CCPU_INTR_REQ 		DOS_REG_ADDR(CCPU_INTR_REQ)
#define P_CPC_P 		DOS_REG_ADDR(CPC_P)
#define P_CPC_D 		DOS_REG_ADDR(CPC_D)
#define P_CPC_E 		DOS_REG_ADDR(CPC_E)
#define P_CPC_W 		DOS_REG_ADDR(CPC_W)
#define P_CINDEX0_REG 		DOS_REG_ADDR(CINDEX0_REG)
#define P_CINDEX1_REG 		DOS_REG_ADDR(CINDEX1_REG)
#define P_CINDEX2_REG 		DOS_REG_ADDR(CINDEX2_REG)
#define P_CINDEX3_REG 		DOS_REG_ADDR(CINDEX3_REG)
#define P_CINDEX4_REG 		DOS_REG_ADDR(CINDEX4_REG)
#define P_CINDEX5_REG 		DOS_REG_ADDR(CINDEX5_REG)
#define P_CINDEX6_REG 		DOS_REG_ADDR(CINDEX6_REG)
#define P_CINDEX7_REG 		DOS_REG_ADDR(CINDEX7_REG)
#define P_CMIN_REG 		DOS_REG_ADDR(CMIN_REG)
#define P_CMAX_REG 		DOS_REG_ADDR(CMAX_REG)
#define P_CBREAK0_REG 		DOS_REG_ADDR(CBREAK0_REG)
#define P_CBREAK1_REG 		DOS_REG_ADDR(CBREAK1_REG)
#define P_CBREAK2_REG 		DOS_REG_ADDR(CBREAK2_REG)
#define P_CBREAK3_REG 		DOS_REG_ADDR(CBREAK3_REG)
#define P_CBREAK_TYPE 		DOS_REG_ADDR(CBREAK_TYPE)
#define P_CBREAK_CTRL 		DOS_REG_ADDR(CBREAK_CTRL)
#define P_CBREAK_STAUTS 		DOS_REG_ADDR(CBREAK_STAUTS)
#define P_CDB_ADDR_REG 		DOS_REG_ADDR(CDB_ADDR_REG)
#define P_CDB_DATA_REG 		DOS_REG_ADDR(CDB_DATA_REG)
#define P_CDB_CTRL 		DOS_REG_ADDR(CDB_CTRL)
#define P_CSFTINT0 		DOS_REG_ADDR(CSFTINT0)
#define P_CSFTINT1 		DOS_REG_ADDR(CSFTINT1)
#define P_IMEM_DMA_CTRL 		DOS_REG_ADDR(IMEM_DMA_CTRL)
#define P_IMEM_DMA_ADR 		DOS_REG_ADDR(IMEM_DMA_ADR)
#define P_IMEM_DMA_COUNT 		DOS_REG_ADDR(IMEM_DMA_COUNT)
#define P_WRRSP_IMEM 		DOS_REG_ADDR(WRRSP_IMEM)
#define P_LMEM_DMA_CTRL 		DOS_REG_ADDR(LMEM_DMA_CTRL)
#define P_LMEM_DMA_ADR 		DOS_REG_ADDR(LMEM_DMA_ADR)
#define P_LMEM_DMA_COUNT 		DOS_REG_ADDR(LMEM_DMA_COUNT)
#define P_WRRSP_LMEM 		DOS_REG_ADDR(WRRSP_LMEM)
#define P_MAC_CTRL1 		DOS_REG_ADDR(MAC_CTRL1)
#define P_ACC0REG1 		DOS_REG_ADDR(ACC0REG1)
#define P_ACC1REG1 		DOS_REG_ADDR(ACC1REG1)
#define P_MAC_CTRL2 		DOS_REG_ADDR(MAC_CTRL2)
#define P_ACC0REG2 		DOS_REG_ADDR(ACC0REG2)
#define P_ACC1REG2 		DOS_REG_ADDR(ACC1REG2)
#define P_CPU_TRACE 		DOS_REG_ADDR(CPU_TRACE)
#define P_DOS_SW_RESET0 		CBUS_REG_ADDR(DOS_SW_RESET0)
#define P_DOS_GCLK_EN0 		CBUS_REG_ADDR(DOS_GCLK_EN0)
#define P_DOS_GEN_CTRL0 		CBUS_REG_ADDR(DOS_GEN_CTRL0)
#define P_DOS_APB_ERR_CTRL 		CBUS_REG_ADDR(DOS_APB_ERR_CTRL)
#define P_DOS_APB_ERR_STAT 		CBUS_REG_ADDR(DOS_APB_ERR_STAT)
#define P_DOS_SCRATCH0 		CBUS_REG_ADDR(DOS_SCRATCH0)
#define P_DOS_SCRATCH1 		CBUS_REG_ADDR(DOS_SCRATCH1)
#define P_DOS_SCRATCH2 		CBUS_REG_ADDR(DOS_SCRATCH2)
#define P_DOS_SCRATCH3 		CBUS_REG_ADDR(DOS_SCRATCH3)
#define P_DOS_SCRATCH4 		CBUS_REG_ADDR(DOS_SCRATCH4)
#define P_DOS_SCRATCH5 		CBUS_REG_ADDR(DOS_SCRATCH5)
#define P_DOS_SCRATCH6 		CBUS_REG_ADDR(DOS_SCRATCH6)
#define P_DOS_SCRATCH7 		CBUS_REG_ADDR(DOS_SCRATCH7)
#define P_DOS_SCRATCH8 		CBUS_REG_ADDR(DOS_SCRATCH8)
#define P_DOS_SCRATCH9 		CBUS_REG_ADDR(DOS_SCRATCH9)
#define P_DOS_SCRATCH10 		CBUS_REG_ADDR(DOS_SCRATCH10)
#define P_DOS_SCRATCH11 		CBUS_REG_ADDR(DOS_SCRATCH11)
#define P_DOS_SCRATCH12 		CBUS_REG_ADDR(DOS_SCRATCH12)
#define P_DOS_SCRATCH13 		CBUS_REG_ADDR(DOS_SCRATCH13)
#define P_DOS_SCRATCH14 		CBUS_REG_ADDR(DOS_SCRATCH14)
#define P_DOS_SCRATCH15 		CBUS_REG_ADDR(DOS_SCRATCH15)
#define P_DOS_SCRATCH16 		CBUS_REG_ADDR(DOS_SCRATCH16)
#define P_DOS_SCRATCH17 		CBUS_REG_ADDR(DOS_SCRATCH17)
#define P_DOS_SCRATCH18 		CBUS_REG_ADDR(DOS_SCRATCH18)
#define P_DOS_SCRATCH19 		CBUS_REG_ADDR(DOS_SCRATCH19)
#define P_DOS_SCRATCH20 		CBUS_REG_ADDR(DOS_SCRATCH20)
#define P_DOS_SCRATCH21 		CBUS_REG_ADDR(DOS_SCRATCH21)
#define P_DOS_SCRATCH22 		CBUS_REG_ADDR(DOS_SCRATCH22)
#define P_DOS_SCRATCH23 		CBUS_REG_ADDR(DOS_SCRATCH23)
#define P_DOS_SCRATCH24 		CBUS_REG_ADDR(DOS_SCRATCH24)
#define P_DOS_SCRATCH25 		CBUS_REG_ADDR(DOS_SCRATCH25)
#define P_DOS_SCRATCH26 		CBUS_REG_ADDR(DOS_SCRATCH26)
#define P_DOS_SCRATCH27 		CBUS_REG_ADDR(DOS_SCRATCH27)
#define P_DOS_SCRATCH28 		CBUS_REG_ADDR(DOS_SCRATCH28)
#define P_DOS_SCRATCH29 		CBUS_REG_ADDR(DOS_SCRATCH29)
#define P_DOS_SCRATCH30 		CBUS_REG_ADDR(DOS_SCRATCH30)
#define P_DOS_SCRATCH31 		CBUS_REG_ADDR(DOS_SCRATCH31)
#define P_AIU_958_BPF 		CBUS_REG_ADDR(AIU_958_BPF)
#define P_AIU_958_BRST 		CBUS_REG_ADDR(AIU_958_BRST)
#define P_AIU_958_LENGTH 		CBUS_REG_ADDR(AIU_958_LENGTH)
#define P_AIU_958_PADDSIZE 		CBUS_REG_ADDR(AIU_958_PADDSIZE)
#define P_AIU_958_MISC 		CBUS_REG_ADDR(AIU_958_MISC)
#define P_AIU_958_FORCE_LEFT 		CBUS_REG_ADDR(AIU_958_FORCE_LEFT)
#define P_AIU_958_DISCARD_NUM 		CBUS_REG_ADDR(AIU_958_DISCARD_NUM)
#define P_AIU_958_DCU_FF_CTRL 		CBUS_REG_ADDR(AIU_958_DCU_FF_CTRL)
#define P_AIU_958_CHSTAT_L0 		CBUS_REG_ADDR(AIU_958_CHSTAT_L0)
#define P_AIU_958_CHSTAT_L1 		CBUS_REG_ADDR(AIU_958_CHSTAT_L1)
#define P_AIU_958_CTRL 		CBUS_REG_ADDR(AIU_958_CTRL)
#define P_AIU_958_RPT 		CBUS_REG_ADDR(AIU_958_RPT)
#define P_AIU_I2S_MUTE_SWAP 		CBUS_REG_ADDR(AIU_I2S_MUTE_SWAP)
#define P_AIU_I2S_SOURCE_DESC 		CBUS_REG_ADDR(AIU_I2S_SOURCE_DESC)
#define P_AIU_I2S_MED_CTRL 		CBUS_REG_ADDR(AIU_I2S_MED_CTRL)
#define P_AIU_I2S_MED_THRESH 		CBUS_REG_ADDR(AIU_I2S_MED_THRESH)
#define P_AIU_I2S_DAC_CFG 		CBUS_REG_ADDR(AIU_I2S_DAC_CFG)
#define P_AIU_I2S_SYNC 		CBUS_REG_ADDR(AIU_I2S_SYNC)
#define P_AIU_I2S_MISC 		CBUS_REG_ADDR(AIU_I2S_MISC)
#define P_AIU_I2S_OUT_CFG 		CBUS_REG_ADDR(AIU_I2S_OUT_CFG)
#define P_AIU_I2S_FF_CTRL 		CBUS_REG_ADDR(AIU_I2S_FF_CTRL)
#define P_AIU_RST_SOFT 		CBUS_REG_ADDR(AIU_RST_SOFT)
#define P_AIU_CLK_CTRL 		CBUS_REG_ADDR(AIU_CLK_CTRL)
#define P_AIU_MIX_ADCCFG 		CBUS_REG_ADDR(AIU_MIX_ADCCFG)
#define P_AIU_MIX_CTRL 		CBUS_REG_ADDR(AIU_MIX_CTRL)
#define P_AIU_CLK_CTRL_MORE 		CBUS_REG_ADDR(AIU_CLK_CTRL_MORE)
#define P_AIU_958_POP 		CBUS_REG_ADDR(AIU_958_POP)
#define P_AIU_MIX_GAIN 		CBUS_REG_ADDR(AIU_MIX_GAIN)
#define P_AIU_958_SYNWORD1 		CBUS_REG_ADDR(AIU_958_SYNWORD1)
#define P_AIU_958_SYNWORD2 		CBUS_REG_ADDR(AIU_958_SYNWORD2)
#define P_AIU_958_SYNWORD3 		CBUS_REG_ADDR(AIU_958_SYNWORD3)
#define P_AIU_958_SYNWORD1_MASK 		CBUS_REG_ADDR(AIU_958_SYNWORD1_MASK)
#define P_AIU_958_SYNWORD2_MASK 		CBUS_REG_ADDR(AIU_958_SYNWORD2_MASK)
#define P_AIU_958_SYNWORD3_MASK 		CBUS_REG_ADDR(AIU_958_SYNWORD3_MASK)
#define P_AIU_958_FFRDOUT_THD 		CBUS_REG_ADDR(AIU_958_FFRDOUT_THD)
#define P_AIU_958_LENGTH_PER_PAUSE 		CBUS_REG_ADDR(AIU_958_LENGTH_PER_PAUSE)
#define P_AIU_958_PAUSE_NUM 		CBUS_REG_ADDR(AIU_958_PAUSE_NUM)
#define P_AIU_958_PAUSE_PAYLOAD 		CBUS_REG_ADDR(AIU_958_PAUSE_PAYLOAD)
#define P_AIU_958_AUTO_PAUSE 		CBUS_REG_ADDR(AIU_958_AUTO_PAUSE)
#define P_AIU_958_PAUSE_PD_LENGTH 		CBUS_REG_ADDR(AIU_958_PAUSE_PD_LENGTH)
#define P_AIU_CODEC_DAC_LRCLK_CTRL 		CBUS_REG_ADDR(AIU_CODEC_DAC_LRCLK_CTRL)
#define P_AIU_CODEC_ADC_LRCLK_CTRL 		CBUS_REG_ADDR(AIU_CODEC_ADC_LRCLK_CTRL)
#define P_AIU_HDMI_CLK_DATA_CTRL 		CBUS_REG_ADDR(AIU_HDMI_CLK_DATA_CTRL)
#define P_AIU_CODEC_CLK_DATA_CTRL 		CBUS_REG_ADDR(AIU_CODEC_CLK_DATA_CTRL)
#define P_AIU_958_CHSTAT_R0 		CBUS_REG_ADDR(AIU_958_CHSTAT_R0)
#define P_AIU_958_CHSTAT_R1 		CBUS_REG_ADDR(AIU_958_CHSTAT_R1)
#define P_AIU_958_VALID_CTRL 		CBUS_REG_ADDR(AIU_958_VALID_CTRL)
#define P_AIU_AUDIO_AMP_REG0 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG0)
#define P_AIU_AUDIO_AMP_REG1 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG1)
#define P_AIU_AUDIO_AMP_REG2 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG2)
#define P_AIU_AUDIO_AMP_REG3 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG3)
#define P_AIU_AIFIFO2_CTRL 		CBUS_REG_ADDR(AIU_AIFIFO2_CTRL)
#define P_AIU_AIFIFO2_STATUS 		CBUS_REG_ADDR(AIU_AIFIFO2_STATUS)
#define P_AIU_AIFIFO2_GBIT 		CBUS_REG_ADDR(AIU_AIFIFO2_GBIT)
#define P_AIU_AIFIFO2_CLB 		CBUS_REG_ADDR(AIU_AIFIFO2_CLB)
#define P_AIU_CRC_CTRL 		CBUS_REG_ADDR(AIU_CRC_CTRL)
#define P_AIU_CRC_STATUS 		CBUS_REG_ADDR(AIU_CRC_STATUS)
#define P_AIU_CRC_SHIFT_REG 		CBUS_REG_ADDR(AIU_CRC_SHIFT_REG)
#define P_AIU_CRC_IREG 		CBUS_REG_ADDR(AIU_CRC_IREG)
#define P_AIU_CRC_CAL_REG1 		CBUS_REG_ADDR(AIU_CRC_CAL_REG1)
#define P_AIU_CRC_CAL_REG0 		CBUS_REG_ADDR(AIU_CRC_CAL_REG0)
#define P_AIU_CRC_POLY_COEF1 		CBUS_REG_ADDR(AIU_CRC_POLY_COEF1)
#define P_AIU_CRC_POLY_COEF0 		CBUS_REG_ADDR(AIU_CRC_POLY_COEF0)
#define P_AIU_CRC_BIT_SIZE1 		CBUS_REG_ADDR(AIU_CRC_BIT_SIZE1)
#define P_AIU_CRC_BIT_SIZE0 		CBUS_REG_ADDR(AIU_CRC_BIT_SIZE0)
#define P_AIU_CRC_BIT_CNT1 		CBUS_REG_ADDR(AIU_CRC_BIT_CNT1)
#define P_AIU_CRC_BIT_CNT0 		CBUS_REG_ADDR(AIU_CRC_BIT_CNT0)
#define P_AIU_AMCLK_GATE_HI 		CBUS_REG_ADDR(AIU_AMCLK_GATE_HI)
#define P_AIU_AMCLK_GATE_LO 		CBUS_REG_ADDR(AIU_AMCLK_GATE_LO)
#define P_AIU_AMCLK_MSR 		CBUS_REG_ADDR(AIU_AMCLK_MSR)
#define P_AIU_AUDAC_CTRL0 		CBUS_REG_ADDR(AIU_AUDAC_CTRL0)
#define P_AIU_AUDAC_CTRL1 		CBUS_REG_ADDR(AIU_AUDAC_CTRL1)
#define P_AIU_DELTA_SIGMA0 		CBUS_REG_ADDR(AIU_DELTA_SIGMA0)
#define P_AIU_DELTA_SIGMA1 		CBUS_REG_ADDR(AIU_DELTA_SIGMA1)
#define P_AIU_DELTA_SIGMA2 		CBUS_REG_ADDR(AIU_DELTA_SIGMA2)
#define P_AIU_DELTA_SIGMA3 		CBUS_REG_ADDR(AIU_DELTA_SIGMA3)
#define P_AIU_DELTA_SIGMA4 		CBUS_REG_ADDR(AIU_DELTA_SIGMA4)
#define P_AIU_DELTA_SIGMA5 		CBUS_REG_ADDR(AIU_DELTA_SIGMA5)
#define P_AIU_DELTA_SIGMA6 		CBUS_REG_ADDR(AIU_DELTA_SIGMA6)
#define P_AIU_DELTA_SIGMA7 		CBUS_REG_ADDR(AIU_DELTA_SIGMA7)
#define P_AIU_DELTA_SIGMA_LCNTS 		CBUS_REG_ADDR(AIU_DELTA_SIGMA_LCNTS)
#define P_AIU_DELTA_SIGMA_RCNTS 		CBUS_REG_ADDR(AIU_DELTA_SIGMA_RCNTS)
#define P_AIU_MEM_I2S_START_PTR 		CBUS_REG_ADDR(AIU_MEM_I2S_START_PTR)
#define P_AIU_MEM_I2S_RD_PTR 		CBUS_REG_ADDR(AIU_MEM_I2S_RD_PTR)
#define P_AIU_MEM_I2S_END_PTR 		CBUS_REG_ADDR(AIU_MEM_I2S_END_PTR)
#define P_AIU_MEM_I2S_MASKS 		CBUS_REG_ADDR(AIU_MEM_I2S_MASKS)
#define P_AIU_MEM_I2S_CONTROL 		CBUS_REG_ADDR(AIU_MEM_I2S_CONTROL)
#define P_AIU_MEM_IEC958_START_PTR 		CBUS_REG_ADDR(AIU_MEM_IEC958_START_PTR)
#define P_AIU_MEM_IEC958_RD_PTR 		CBUS_REG_ADDR(AIU_MEM_IEC958_RD_PTR)
#define P_AIU_MEM_IEC958_END_PTR 		CBUS_REG_ADDR(AIU_MEM_IEC958_END_PTR)
#define P_AIU_MEM_IEC958_MASKS 		CBUS_REG_ADDR(AIU_MEM_IEC958_MASKS)
#define P_AIU_MEM_IEC958_CONTROL 		CBUS_REG_ADDR(AIU_MEM_IEC958_CONTROL)
#define P_AIU_MEM_AIFIFO2_START_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_START_PTR)
#define P_AIU_MEM_AIFIFO2_CURR_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CURR_PTR)
#define P_AIU_MEM_AIFIFO2_END_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_END_PTR)
#define P_AIU_MEM_AIFIFO2_BYTES_AVAIL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BYTES_AVAIL)
#define P_AIU_MEM_AIFIFO2_CONTROL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CONTROL)
#define P_AIU_MEM_AIFIFO2_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_WP)
#define P_AIU_MEM_AIFIFO2_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_RP)
#define P_AIU_MEM_AIFIFO2_LEVEL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_LEVEL)
#define P_AIU_MEM_AIFIFO2_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_CNTL)
#define P_AIU_MEM_I2S_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_I2S_MAN_WP)
#define P_AIU_MEM_I2S_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_I2S_MAN_RP)
#define P_AIU_MEM_I2S_LEVEL 		CBUS_REG_ADDR(AIU_MEM_I2S_LEVEL)
#define P_AIU_MEM_I2S_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_I2S_BUF_CNTL)
#define P_AIU_MEM_I2S_BUF_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_I2S_BUF_WRAP_COUNT)
#define P_AIU_MEM_I2S_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_I2S_MEM_CTL)
#define P_AIU_MEM_IEC958_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_IEC958_MEM_CTL)
#define P_AIU_MEM_IEC958_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_IEC958_WRAP_COUNT)
#define P_AIU_MEM_IEC958_IRQ_LEVEL 		CBUS_REG_ADDR(AIU_MEM_IEC958_IRQ_LEVEL)
#define P_AIU_MEM_IEC958_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_WP)
#define P_AIU_MEM_IEC958_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_RP)
#define P_AIU_MEM_IEC958_LEVEL 		CBUS_REG_ADDR(AIU_MEM_IEC958_LEVEL)
#define P_AIU_MEM_IEC958_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_IEC958_BUF_CNTL)
#define P_AIU_AIFIFO_CTRL 		CBUS_REG_ADDR(AIU_AIFIFO_CTRL)
#define P_AIU_AIFIFO_STATUS 		CBUS_REG_ADDR(AIU_AIFIFO_STATUS)
#define P_AIU_AIFIFO_GBIT 		CBUS_REG_ADDR(AIU_AIFIFO_GBIT)
#define P_AIU_AIFIFO_CLB 		CBUS_REG_ADDR(AIU_AIFIFO_CLB)
#define P_AIU_MEM_AIFIFO_START_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_START_PTR)
#define P_AIU_MEM_AIFIFO_CURR_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_CURR_PTR)
#define P_AIU_MEM_AIFIFO_END_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_END_PTR)
#define P_AIU_MEM_AIFIFO_BYTES_AVAIL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_BYTES_AVAIL)
#define P_AIU_MEM_AIFIFO_CONTROL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_CONTROL)
#define P_AIU_MEM_AIFIFO_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_WP)
#define P_AIU_MEM_AIFIFO_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_RP)
#define P_AIU_MEM_AIFIFO_LEVEL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_LEVEL)
#define P_AIU_MEM_AIFIFO_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_CNTL)
#define P_AIU_MEM_AIFIFO_BUF_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_WRAP_COUNT)
#define P_AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_WRAP_COUNT)
#define P_AIU_MEM_AIFIFO_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_MEM_CTL)
#define P_AIFIFO_TIME_STAMP_CNTL 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_CNTL)
#define P_AIFIFO_TIME_STAMP_SYNC_0 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_0)
#define P_AIFIFO_TIME_STAMP_SYNC_1 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_1)
#define P_AIFIFO_TIME_STAMP_0 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_0)
#define P_AIFIFO_TIME_STAMP_1 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_1)
#define P_AIFIFO_TIME_STAMP_2 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_2)
#define P_AIFIFO_TIME_STAMP_3 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_3)
#define P_AIFIFO_TIME_STAMP_LENGTH 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_LENGTH)
#define P_AIFIFO2_TIME_STAMP_CNTL 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_CNTL)
#define P_AIFIFO2_TIME_STAMP_SYNC_0 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_0)
#define P_AIFIFO2_TIME_STAMP_SYNC_1 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_1)
#define P_AIFIFO2_TIME_STAMP_0 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_0)
#define P_AIFIFO2_TIME_STAMP_1 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_1)
#define P_AIFIFO2_TIME_STAMP_2 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_2)
#define P_AIFIFO2_TIME_STAMP_3 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_3)
#define P_AIFIFO2_TIME_STAMP_LENGTH 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_LENGTH)
#define P_IEC958_TIME_STAMP_CNTL 		CBUS_REG_ADDR(IEC958_TIME_STAMP_CNTL)
#define P_IEC958_TIME_STAMP_SYNC_0 		CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_0)
#define P_IEC958_TIME_STAMP_SYNC_1 		CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_1)
#define P_IEC958_TIME_STAMP_0 		CBUS_REG_ADDR(IEC958_TIME_STAMP_0)
#define P_IEC958_TIME_STAMP_1 		CBUS_REG_ADDR(IEC958_TIME_STAMP_1)
#define P_IEC958_TIME_STAMP_2 		CBUS_REG_ADDR(IEC958_TIME_STAMP_2)
#define P_IEC958_TIME_STAMP_3 		CBUS_REG_ADDR(IEC958_TIME_STAMP_3)
#define P_IEC958_TIME_STAMP_LENGTH 		CBUS_REG_ADDR(IEC958_TIME_STAMP_LENGTH)
#define P_AIU_MEM_AIFIFO2_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MEM_CTL)
#define P_AIU_I2S_CBUS_DDR_CNTL 		CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_CNTL)
#define P_AIU_I2S_CBUS_DDR_WDATA 		CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_WDATA)
#define P_AIU_I2S_CBUS_DDR_ADDR 		CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_ADDR)
#define P_AIADR 		CBUS_REG_ADDR(AIADR)
#define P_AICSR 		CBUS_REG_ADDR(AICSR)
#define P_AIDAT 		CBUS_REG_ADDR(AIDAT)
#define P_AIGBIT 		CBUS_REG_ADDR(AIGBIT)
#define P_AICLB 		CBUS_REG_ADDR(AICLB)
#define P_HD0 		CBUS_REG_ADDR(HD0)
#define P_HD1 		CBUS_REG_ADDR(HD1)
#define P_SHD0 		CBUS_REG_ADDR(SHD0)
#define P_SHD1 		CBUS_REG_ADDR(SHD1)
#define P_SYND 		CBUS_REG_ADDR(SYND)
#define P_ECDCT 		CBUS_REG_ADDR(ECDCT)
#define P_ECDSTAT 		CBUS_REG_ADDR(ECDSTAT)
#define P_CTR0 		CBUS_REG_ADDR(CTR0)
#define P_CTR1 		CBUS_REG_ADDR(CTR1)
#define P_CTR2 		CBUS_REG_ADDR(CTR2)
#define P_STAT0 		CBUS_REG_ADDR(STAT0)
#define P_INT 		CBUS_REG_ADDR(INT)
#define P_TCTR0 		CBUS_REG_ADDR(TCTR0)
#define P_TSTAT0 		CBUS_REG_ADDR(TSTAT0)
#define P_TSTAT1 		CBUS_REG_ADDR(TSTAT1)
#define P_VPP_DUMMY_DATA 		CBUS_REG_ADDR(VPP_DUMMY_DATA)
#define P_VPP_LINE_IN_LENGTH 		CBUS_REG_ADDR(VPP_LINE_IN_LENGTH)
#define P_VPP_PIC_IN_HEIGHT 		CBUS_REG_ADDR(VPP_PIC_IN_HEIGHT)
#define P_VPP_SCALE_COEF_IDX 		CBUS_REG_ADDR(VPP_SCALE_COEF_IDX)
#define P_VPP_SCALE_COEF 		CBUS_REG_ADDR(VPP_SCALE_COEF)
#define P_VPP_VSC_REGION12_STARTP 		CBUS_REG_ADDR(VPP_VSC_REGION12_STARTP)
#define P_VPP_VSC_REGION34_STARTP 		CBUS_REG_ADDR(VPP_VSC_REGION34_STARTP)
#define P_VPP_VSC_REGION4_ENDP 		CBUS_REG_ADDR(VPP_VSC_REGION4_ENDP)
#define P_VPP_VSC_START_PHASE_STEP 		CBUS_REG_ADDR(VPP_VSC_START_PHASE_STEP)
#define P_VPP_VSC_REGION0_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_VSC_REGION0_PHASE_SLOPE)
#define P_VPP_VSC_REGION1_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_VSC_REGION1_PHASE_SLOPE)
#define P_VPP_VSC_REGION3_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_VSC_REGION3_PHASE_SLOPE)
#define P_VPP_VSC_REGION4_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_VSC_REGION4_PHASE_SLOPE)
#define P_VPP_VSC_PHASE_CTRL 		CBUS_REG_ADDR(VPP_VSC_PHASE_CTRL)
#define P_VPP_VSC_INI_PHASE 		CBUS_REG_ADDR(VPP_VSC_INI_PHASE)
#define P_VPP_HSC_REGION12_STARTP 		CBUS_REG_ADDR(VPP_HSC_REGION12_STARTP)
#define P_VPP_HSC_REGION34_STARTP 		CBUS_REG_ADDR(VPP_HSC_REGION34_STARTP)
#define P_VPP_HSC_REGION4_ENDP 		CBUS_REG_ADDR(VPP_HSC_REGION4_ENDP)
#define P_VPP_HSC_START_PHASE_STEP 		CBUS_REG_ADDR(VPP_HSC_START_PHASE_STEP)
#define P_VPP_HSC_REGION0_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_HSC_REGION0_PHASE_SLOPE)
#define P_VPP_HSC_REGION1_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_HSC_REGION1_PHASE_SLOPE)
#define P_VPP_HSC_REGION3_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_HSC_REGION3_PHASE_SLOPE)
#define P_VPP_HSC_REGION4_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_HSC_REGION4_PHASE_SLOPE)
#define P_VPP_HSC_PHASE_CTRL 		CBUS_REG_ADDR(VPP_HSC_PHASE_CTRL)
#define P_VPP_SC_MISC 		CBUS_REG_ADDR(VPP_SC_MISC)
#define P_VPP_PREBLEND_VD1_H_START_END 		CBUS_REG_ADDR(VPP_PREBLEND_VD1_H_START_END)
#define P_VPP_PREBLEND_VD1_V_START_END 		CBUS_REG_ADDR(VPP_PREBLEND_VD1_V_START_END)
#define P_VPP_POSTBLEND_VD1_H_START_END 		CBUS_REG_ADDR(VPP_POSTBLEND_VD1_H_START_END)
#define P_VPP_POSTBLEND_VD1_V_START_END 		CBUS_REG_ADDR(VPP_POSTBLEND_VD1_V_START_END)
#define P_VPP_BLEND_VD2_H_START_END 		CBUS_REG_ADDR(VPP_BLEND_VD2_H_START_END)
#define P_VPP_BLEND_VD2_V_START_END 		CBUS_REG_ADDR(VPP_BLEND_VD2_V_START_END)
#define P_VPP_PREBLEND_H_SIZE 		CBUS_REG_ADDR(VPP_PREBLEND_H_SIZE)
#define P_VPP_POSTBLEND_H_SIZE 		CBUS_REG_ADDR(VPP_POSTBLEND_H_SIZE)
#define P_VPP_HOLD_LINES 		CBUS_REG_ADDR(VPP_HOLD_LINES)
#define P_VPP_BLEND_ONECOLOR_CTRL 		CBUS_REG_ADDR(VPP_BLEND_ONECOLOR_CTRL)
#define P_VPP_PREBLEND_CURRENT_XY 		CBUS_REG_ADDR(VPP_PREBLEND_CURRENT_XY)
#define P_VPP_POSTBLEND_CURRENT_XY 		CBUS_REG_ADDR(VPP_POSTBLEND_CURRENT_XY)
#define P_VPP_MISC 		CBUS_REG_ADDR(VPP_MISC)
#define P_VPP_OFIFO_SIZE 		CBUS_REG_ADDR(VPP_OFIFO_SIZE)
#define P_VPP_FIFO_STATUS 		CBUS_REG_ADDR(VPP_FIFO_STATUS)
#define P_VPP_SMOKE_CTRL 		CBUS_REG_ADDR(VPP_SMOKE_CTRL)
#define P_VPP_SMOKE1_VAL 		CBUS_REG_ADDR(VPP_SMOKE1_VAL)
#define P_VPP_SMOKE2_VAL 		CBUS_REG_ADDR(VPP_SMOKE2_VAL)
#define P_VPP_SMOKE3_VAL 		CBUS_REG_ADDR(VPP_SMOKE3_VAL)
#define P_VPP_SMOKE1_H_START_END 		CBUS_REG_ADDR(VPP_SMOKE1_H_START_END)
#define P_VPP_SMOKE1_V_START_END 		CBUS_REG_ADDR(VPP_SMOKE1_V_START_END)
#define P_VPP_SMOKE2_H_START_END 		CBUS_REG_ADDR(VPP_SMOKE2_H_START_END)
#define P_VPP_SMOKE2_V_START_END 		CBUS_REG_ADDR(VPP_SMOKE2_V_START_END)
#define P_VPP_SMOKE3_H_START_END 		CBUS_REG_ADDR(VPP_SMOKE3_H_START_END)
#define P_VPP_SMOKE3_V_START_END 		CBUS_REG_ADDR(VPP_SMOKE3_V_START_END)
#define P_VPP_SCO_FIFO_CTRL 		CBUS_REG_ADDR(VPP_SCO_FIFO_CTRL)
#define P_VPP_VADJ_CTRL 		CBUS_REG_ADDR(VPP_VADJ_CTRL)
#define P_VPP_VADJ1_Y 		CBUS_REG_ADDR(VPP_VADJ1_Y)
#define P_VPP_VADJ1_MA_MB 		CBUS_REG_ADDR(VPP_VADJ1_MA_MB)
#define P_VPP_VADJ1_MC_MD 		CBUS_REG_ADDR(VPP_VADJ1_MC_MD)
#define P_VPP_VADJ2_Y 		CBUS_REG_ADDR(VPP_VADJ2_Y)
#define P_VPP_VADJ2_MA_MB 		CBUS_REG_ADDR(VPP_VADJ2_MA_MB)
#define P_VPP_VADJ2_MC_MD 		CBUS_REG_ADDR(VPP_VADJ2_MC_MD)
#define P_VPP_HSHARP_CTRL 		CBUS_REG_ADDR(VPP_HSHARP_CTRL)
#define P_VPP_HSHARP_LUMA_THRESH01 		CBUS_REG_ADDR(VPP_HSHARP_LUMA_THRESH01)
#define P_VPP_HSHARP_LUMA_THRESH23 		CBUS_REG_ADDR(VPP_HSHARP_LUMA_THRESH23)
#define P_VPP_HSHARP_CHROMA_THRESH01 		CBUS_REG_ADDR(VPP_HSHARP_CHROMA_THRESH01)
#define P_VPP_HSHARP_CHROMA_THRESH23 		CBUS_REG_ADDR(VPP_HSHARP_CHROMA_THRESH23)
#define P_VPP_HSHARP_LUMA_GAIN 		CBUS_REG_ADDR(VPP_HSHARP_LUMA_GAIN)
#define P_VPP_HSHARP_CHROMA_GAIN 		CBUS_REG_ADDR(VPP_HSHARP_CHROMA_GAIN)
#define P_VPP_MATRIX_CTRL 		CBUS_REG_ADDR(VPP_MATRIX_CTRL)
#define P_VPP_MATRIX_COEF00_01 		CBUS_REG_ADDR(VPP_MATRIX_COEF00_01)
#define P_VPP_MATRIX_COEF02_10 		CBUS_REG_ADDR(VPP_MATRIX_COEF02_10)
#define P_VPP_MATRIX_COEF11_12 		CBUS_REG_ADDR(VPP_MATRIX_COEF11_12)
#define P_VPP_MATRIX_COEF20_21 		CBUS_REG_ADDR(VPP_MATRIX_COEF20_21)
#define P_VPP_MATRIX_COEF22 		CBUS_REG_ADDR(VPP_MATRIX_COEF22)
#define P_VPP_MATRIX_OFFSET0_1 		CBUS_REG_ADDR(VPP_MATRIX_OFFSET0_1)
#define P_VPP_MATRIX_OFFSET2 		CBUS_REG_ADDR(VPP_MATRIX_OFFSET2)
#define P_VPP_MATRIX_PRE_OFFSET0_1 		CBUS_REG_ADDR(VPP_MATRIX_PRE_OFFSET0_1)
#define P_VPP_MATRIX_PRE_OFFSET2 		CBUS_REG_ADDR(VPP_MATRIX_PRE_OFFSET2)
#define P_VPP_DUMMY_DATA1 		CBUS_REG_ADDR(VPP_DUMMY_DATA1)
#define P_VPP_GAINOFF_CTRL0 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL0)
#define P_VPP_GAINOFF_CTRL1 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL1)
#define P_VPP_GAINOFF_CTRL2 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL2)
#define P_VPP_GAINOFF_CTRL3 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL3)
#define P_VPP_GAINOFF_CTRL4 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL4)
#define P_VPP_CHROMA_ADDR_PORT 		CBUS_REG_ADDR(VPP_CHROMA_ADDR_PORT)
#define P_VPP_CHROMA_DATA_PORT 		CBUS_REG_ADDR(VPP_CHROMA_DATA_PORT)
#define P_VPP_GCLK_CTRL0 		CBUS_REG_ADDR(VPP_GCLK_CTRL0)
#define P_VPP_GCLK_CTRL1 		CBUS_REG_ADDR(VPP_GCLK_CTRL1)
#define P_VPP_SC_GCLK_CTRL 		CBUS_REG_ADDR(VPP_SC_GCLK_CTRL)
#define P_VPP_BLACKEXT_CTRL 		CBUS_REG_ADDR(VPP_BLACKEXT_CTRL)
#define P_VPP_DNLP_CTRL_00 		CBUS_REG_ADDR(VPP_DNLP_CTRL_00)
#define P_VPP_DNLP_CTRL_01 		CBUS_REG_ADDR(VPP_DNLP_CTRL_01)
#define P_VPP_DNLP_CTRL_02 		CBUS_REG_ADDR(VPP_DNLP_CTRL_02)
#define P_VPP_DNLP_CTRL_03 		CBUS_REG_ADDR(VPP_DNLP_CTRL_03)
#define P_VPP_DNLP_CTRL_04 		CBUS_REG_ADDR(VPP_DNLP_CTRL_04)
#define P_VPP_DNLP_CTRL_05 		CBUS_REG_ADDR(VPP_DNLP_CTRL_05)
#define P_VPP_DNLP_CTRL_06 		CBUS_REG_ADDR(VPP_DNLP_CTRL_06)
#define P_VPP_DNLP_CTRL_07 		CBUS_REG_ADDR(VPP_DNLP_CTRL_07)
#define P_VPP_DNLP_CTRL_08 		CBUS_REG_ADDR(VPP_DNLP_CTRL_08)
#define P_VPP_DNLP_CTRL_09 		CBUS_REG_ADDR(VPP_DNLP_CTRL_09)
#define P_VPP_DNLP_CTRL_10 		CBUS_REG_ADDR(VPP_DNLP_CTRL_10)
#define P_VPP_DNLP_CTRL_11 		CBUS_REG_ADDR(VPP_DNLP_CTRL_11)
#define P_VPP_DNLP_CTRL_12 		CBUS_REG_ADDR(VPP_DNLP_CTRL_12)
#define P_VPP_DNLP_CTRL_13 		CBUS_REG_ADDR(VPP_DNLP_CTRL_13)
#define P_VPP_DNLP_CTRL_14 		CBUS_REG_ADDR(VPP_DNLP_CTRL_14)
#define P_VPP_DNLP_CTRL_15 		CBUS_REG_ADDR(VPP_DNLP_CTRL_15)
#define P_VPP_PEAKING_HGAIN 		CBUS_REG_ADDR(VPP_PEAKING_HGAIN)
#define P_VPP_PEAKING_VGAIN 		CBUS_REG_ADDR(VPP_PEAKING_VGAIN)
#define P_VPP_PEAKING_NLP_1 		CBUS_REG_ADDR(VPP_PEAKING_NLP_1)
#define P_VPP_PEAKING_NLP_2 		CBUS_REG_ADDR(VPP_PEAKING_NLP_2)
#define P_VPP_PEAKING_NLP_3 		CBUS_REG_ADDR(VPP_PEAKING_NLP_3)
#define P_VPP_PEAKING_NLP_4 		CBUS_REG_ADDR(VPP_PEAKING_NLP_4)
#define P_VPP_PEAKING_NLP_5 		CBUS_REG_ADDR(VPP_PEAKING_NLP_5)
#define P_VPP_SHARP_LIMIT 		CBUS_REG_ADDR(VPP_SHARP_LIMIT)
#define P_VPP_VLTI_CTRL 		CBUS_REG_ADDR(VPP_VLTI_CTRL)
#define P_VPP_HLTI_CTRL 		CBUS_REG_ADDR(VPP_HLTI_CTRL)
#define P_VPP_CTI_CTRL 		CBUS_REG_ADDR(VPP_CTI_CTRL)
#define P_VPP_BLUE_STRETCH_1 		CBUS_REG_ADDR(VPP_BLUE_STRETCH_1)
#define P_VPP_BLUE_STRETCH_2 		CBUS_REG_ADDR(VPP_BLUE_STRETCH_2)
#define P_VPP_BLUE_STRETCH_3 		CBUS_REG_ADDR(VPP_BLUE_STRETCH_3)
#define P_VPP_CCORING_CTRL 		CBUS_REG_ADDR(VPP_CCORING_CTRL)
#define P_VPP_VE_ENABLE_CTRL 		CBUS_REG_ADDR(VPP_VE_ENABLE_CTRL)
#define P_VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 		CBUS_REG_ADDR(VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH)
#define P_VPP_VE_DEMO_CENTER_BAR 		CBUS_REG_ADDR(VPP_VE_DEMO_CENTER_BAR)
#define P_VPP_VDO_MEAS_CTRL 		CBUS_REG_ADDR(VPP_VDO_MEAS_CTRL)
#define P_VPP_VDO_MEAS_VS_COUNT_HI 		CBUS_REG_ADDR(VPP_VDO_MEAS_VS_COUNT_HI)
#define P_VPP_VDO_MEAS_VS_COUNT_LO 		CBUS_REG_ADDR(VPP_VDO_MEAS_VS_COUNT_LO)
#define P_VPP2_DUMMY_DATA 		CBUS_REG_ADDR(VPP2_DUMMY_DATA)
#define P_VPP2_LINE_IN_LENGTH 		CBUS_REG_ADDR(VPP2_LINE_IN_LENGTH)
#define P_VPP2_PIC_IN_HEIGHT 		CBUS_REG_ADDR(VPP2_PIC_IN_HEIGHT)
#define P_VPP2_SCALE_COEF_IDX 		CBUS_REG_ADDR(VPP2_SCALE_COEF_IDX)
#define P_VPP2_SCALE_COEF 		CBUS_REG_ADDR(VPP2_SCALE_COEF)
#define P_VPP2_VSC_REGION12_STARTP 		CBUS_REG_ADDR(VPP2_VSC_REGION12_STARTP)
#define P_VPP2_VSC_REGION34_STARTP 		CBUS_REG_ADDR(VPP2_VSC_REGION34_STARTP)
#define P_VPP2_VSC_REGION4_ENDP 		CBUS_REG_ADDR(VPP2_VSC_REGION4_ENDP)
#define P_VPP2_VSC_START_PHASE_STEP 		CBUS_REG_ADDR(VPP2_VSC_START_PHASE_STEP)
#define P_VPP2_VSC_REGION0_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_VSC_REGION0_PHASE_SLOPE)
#define P_VPP2_VSC_REGION1_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_VSC_REGION1_PHASE_SLOPE)
#define P_VPP2_VSC_REGION3_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_VSC_REGION3_PHASE_SLOPE)
#define P_VPP2_VSC_REGION4_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_VSC_REGION4_PHASE_SLOPE)
#define P_VPP2_VSC_PHASE_CTRL 		CBUS_REG_ADDR(VPP2_VSC_PHASE_CTRL)
#define P_VPP2_VSC_INI_PHASE 		CBUS_REG_ADDR(VPP2_VSC_INI_PHASE)
#define P_VPP2_HSC_REGION12_STARTP 		CBUS_REG_ADDR(VPP2_HSC_REGION12_STARTP)
#define P_VPP2_HSC_REGION34_STARTP 		CBUS_REG_ADDR(VPP2_HSC_REGION34_STARTP)
#define P_VPP2_HSC_REGION4_ENDP 		CBUS_REG_ADDR(VPP2_HSC_REGION4_ENDP)
#define P_VPP2_HSC_START_PHASE_STEP 		CBUS_REG_ADDR(VPP2_HSC_START_PHASE_STEP)
#define P_VPP2_HSC_REGION0_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_HSC_REGION0_PHASE_SLOPE)
#define P_VPP2_HSC_REGION1_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_HSC_REGION1_PHASE_SLOPE)
#define P_VPP2_HSC_REGION3_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_HSC_REGION3_PHASE_SLOPE)
#define P_VPP2_HSC_REGION4_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_HSC_REGION4_PHASE_SLOPE)
#define P_VPP2_HSC_PHASE_CTRL 		CBUS_REG_ADDR(VPP2_HSC_PHASE_CTRL)
#define P_VPP2_SC_MISC 		CBUS_REG_ADDR(VPP2_SC_MISC)
#define P_VPP2_PREBLEND_VD1_H_START_END 		CBUS_REG_ADDR(VPP2_PREBLEND_VD1_H_START_END)
#define P_VPP2_PREBLEND_VD1_V_START_END 		CBUS_REG_ADDR(VPP2_PREBLEND_VD1_V_START_END)
#define P_VPP2_POSTBLEND_VD1_H_START_END 		CBUS_REG_ADDR(VPP2_POSTBLEND_VD1_H_START_END)
#define P_VPP2_POSTBLEND_VD1_V_START_END 		CBUS_REG_ADDR(VPP2_POSTBLEND_VD1_V_START_END)
#define P_VPP2_PREBLEND_H_SIZE 		CBUS_REG_ADDR(VPP2_PREBLEND_H_SIZE)
#define P_VPP2_POSTBLEND_H_SIZE 		CBUS_REG_ADDR(VPP2_POSTBLEND_H_SIZE)
#define P_VPP2_HOLD_LINES 		CBUS_REG_ADDR(VPP2_HOLD_LINES)
#define P_VPP2_BLEND_ONECOLOR_CTRL 		CBUS_REG_ADDR(VPP2_BLEND_ONECOLOR_CTRL)
#define P_VPP2_PREBLEND_CURRENT_XY 		CBUS_REG_ADDR(VPP2_PREBLEND_CURRENT_XY)
#define P_VPP2_POSTBLEND_CURRENT_XY 		CBUS_REG_ADDR(VPP2_POSTBLEND_CURRENT_XY)
#define P_VPP2_MISC 		CBUS_REG_ADDR(VPP2_MISC)
#define P_VPP2_OFIFO_SIZE 		CBUS_REG_ADDR(VPP2_OFIFO_SIZE)
#define P_VPP2_FIFO_STATUS 		CBUS_REG_ADDR(VPP2_FIFO_STATUS)
#define P_VPP2_SMOKE_CTRL 		CBUS_REG_ADDR(VPP2_SMOKE_CTRL)
#define P_VPP2_SMOKE1_VAL 		CBUS_REG_ADDR(VPP2_SMOKE1_VAL)
#define P_VPP2_SMOKE2_VAL 		CBUS_REG_ADDR(VPP2_SMOKE2_VAL)
#define P_VPP2_SMOKE1_H_START_END 		CBUS_REG_ADDR(VPP2_SMOKE1_H_START_END)
#define P_VPP2_SMOKE1_V_START_END 		CBUS_REG_ADDR(VPP2_SMOKE1_V_START_END)
#define P_VPP2_SMOKE2_H_START_END 		CBUS_REG_ADDR(VPP2_SMOKE2_H_START_END)
#define P_VPP2_SMOKE2_V_START_END 		CBUS_REG_ADDR(VPP2_SMOKE2_V_START_END)
#define P_VPP2_SCO_FIFO_CTRL 		CBUS_REG_ADDR(VPP2_SCO_FIFO_CTRL)
#define P_VPP2_VADJ_CTRL 		CBUS_REG_ADDR(VPP2_VADJ_CTRL)
#define P_VPP2_VADJ1_Y 		CBUS_REG_ADDR(VPP2_VADJ1_Y)
#define P_VPP2_VADJ1_MA_MB 		CBUS_REG_ADDR(VPP2_VADJ1_MA_MB)
#define P_VPP2_VADJ1_MC_MD 		CBUS_REG_ADDR(VPP2_VADJ1_MC_MD)
#define P_VPP2_VADJ2_Y 		CBUS_REG_ADDR(VPP2_VADJ2_Y)
#define P_VPP2_VADJ2_MA_MB 		CBUS_REG_ADDR(VPP2_VADJ2_MA_MB)
#define P_VPP2_VADJ2_MC_MD 		CBUS_REG_ADDR(VPP2_VADJ2_MC_MD)
#define P_VPP2_HSHARP_CTRL 		CBUS_REG_ADDR(VPP2_HSHARP_CTRL)
#define P_VPP2_HSHARP_LUMA_THRESH01 		CBUS_REG_ADDR(VPP2_HSHARP_LUMA_THRESH01)
#define P_VPP2_HSHARP_LUMA_THRESH23 		CBUS_REG_ADDR(VPP2_HSHARP_LUMA_THRESH23)
#define P_VPP2_HSHARP_CHROMA_THRESH01 		CBUS_REG_ADDR(VPP2_HSHARP_CHROMA_THRESH01)
#define P_VPP2_HSHARP_CHROMA_THRESH23 		CBUS_REG_ADDR(VPP2_HSHARP_CHROMA_THRESH23)
#define P_VPP2_HSHARP_LUMA_GAIN 		CBUS_REG_ADDR(VPP2_HSHARP_LUMA_GAIN)
#define P_VPP2_HSHARP_CHROMA_GAIN 		CBUS_REG_ADDR(VPP2_HSHARP_CHROMA_GAIN)
#define P_VPP2_MATRIX_CTRL 		CBUS_REG_ADDR(VPP2_MATRIX_CTRL)
#define P_VPP2_MATRIX_COEF00_01 		CBUS_REG_ADDR(VPP2_MATRIX_COEF00_01)
#define P_VPP2_MATRIX_COEF02_10 		CBUS_REG_ADDR(VPP2_MATRIX_COEF02_10)
#define P_VPP2_MATRIX_COEF11_12 		CBUS_REG_ADDR(VPP2_MATRIX_COEF11_12)
#define P_VPP2_MATRIX_COEF20_21 		CBUS_REG_ADDR(VPP2_MATRIX_COEF20_21)
#define P_VPP2_MATRIX_COEF22 		CBUS_REG_ADDR(VPP2_MATRIX_COEF22)
#define P_VPP2_MATRIX_OFFSET0_1 		CBUS_REG_ADDR(VPP2_MATRIX_OFFSET0_1)
#define P_VPP2_MATRIX_OFFSET2 		CBUS_REG_ADDR(VPP2_MATRIX_OFFSET2)
#define P_VPP2_MATRIX_PRE_OFFSET0_1 		CBUS_REG_ADDR(VPP2_MATRIX_PRE_OFFSET0_1)
#define P_VPP2_MATRIX_PRE_OFFSET2 		CBUS_REG_ADDR(VPP2_MATRIX_PRE_OFFSET2)
#define P_VPP2_DUMMY_DATA1 		CBUS_REG_ADDR(VPP2_DUMMY_DATA1)
#define P_VPP2_GAINOFF_CTRL0 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL0)
#define P_VPP2_GAINOFF_CTRL1 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL1)
#define P_VPP2_GAINOFF_CTRL2 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL2)
#define P_VPP2_GAINOFF_CTRL3 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL3)
#define P_VPP2_GAINOFF_CTRL4 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL4)
#define P_VPP2_CHROMA_ADDR_PORT 		CBUS_REG_ADDR(VPP2_CHROMA_ADDR_PORT)
#define P_VPP2_CHROMA_DATA_PORT 		CBUS_REG_ADDR(VPP2_CHROMA_DATA_PORT)
#define P_VPP2_GCLK_CTRL0 		CBUS_REG_ADDR(VPP2_GCLK_CTRL0)
#define P_VPP2_GCLK_CTRL1 		CBUS_REG_ADDR(VPP2_GCLK_CTRL1)
#define P_VPP2_SC_GCLK_CTRL 		CBUS_REG_ADDR(VPP2_SC_GCLK_CTRL)
#define P_VPP2_BLACKEXT_CTRL 		CBUS_REG_ADDR(VPP2_BLACKEXT_CTRL)
#define P_VPP2_DNLP_CTRL_00 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_00)
#define P_VPP2_DNLP_CTRL_01 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_01)
#define P_VPP2_DNLP_CTRL_02 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_02)
#define P_VPP2_DNLP_CTRL_03 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_03)
#define P_VPP2_DNLP_CTRL_04 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_04)
#define P_VPP2_DNLP_CTRL_05 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_05)
#define P_VPP2_DNLP_CTRL_06 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_06)
#define P_VPP2_DNLP_CTRL_07 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_07)
#define P_VPP2_DNLP_CTRL_08 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_08)
#define P_VPP2_DNLP_CTRL_09 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_09)
#define P_VPP2_DNLP_CTRL_10 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_10)
#define P_VPP2_DNLP_CTRL_11 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_11)
#define P_VPP2_DNLP_CTRL_12 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_12)
#define P_VPP2_DNLP_CTRL_13 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_13)
#define P_VPP2_DNLP_CTRL_14 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_14)
#define P_VPP2_DNLP_CTRL_15 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_15)
#define P_VPP2_PEAKING_HGAIN 		CBUS_REG_ADDR(VPP2_PEAKING_HGAIN)
#define P_VPP2_PEAKING_VGAIN 		CBUS_REG_ADDR(VPP2_PEAKING_VGAIN)
#define P_VPP2_PEAKING_NLP_1 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_1)
#define P_VPP2_PEAKING_NLP_2 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_2)
#define P_VPP2_PEAKING_NLP_3 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_3)
#define P_VPP2_PEAKING_NLP_4 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_4)
#define P_VPP2_PEAKING_NLP_5 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_5)
#define P_VPP2_SHARP_LIMIT 		CBUS_REG_ADDR(VPP2_SHARP_LIMIT)
#define P_VPP2_VLTI_CTRL 		CBUS_REG_ADDR(VPP2_VLTI_CTRL)
#define P_VPP2_HLTI_CTRL 		CBUS_REG_ADDR(VPP2_HLTI_CTRL)
#define P_VPP2_CTI_CTRL 		CBUS_REG_ADDR(VPP2_CTI_CTRL)
#define P_VPP2_BLUE_STRETCH_1 		CBUS_REG_ADDR(VPP2_BLUE_STRETCH_1)
#define P_VPP2_BLUE_STRETCH_2 		CBUS_REG_ADDR(VPP2_BLUE_STRETCH_2)
#define P_VPP2_BLUE_STRETCH_3 		CBUS_REG_ADDR(VPP2_BLUE_STRETCH_3)
#define P_VPP2_CCORING_CTRL 		CBUS_REG_ADDR(VPP2_CCORING_CTRL)
#define P_VPP2_VE_ENABLE_CTRL 		CBUS_REG_ADDR(VPP2_VE_ENABLE_CTRL)
#define P_VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 		CBUS_REG_ADDR(VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH)
#define P_VPP2_VE_DEMO_CENTER_BAR 		CBUS_REG_ADDR(VPP2_VE_DEMO_CENTER_BAR)
#define P_VPP2_VDO_MEAS_CTRL 		CBUS_REG_ADDR(VPP2_VDO_MEAS_CTRL)
#define P_VPP2_VDO_MEAS_VS_COUNT_HI 		CBUS_REG_ADDR(VPP2_VDO_MEAS_VS_COUNT_HI)
#define P_VPP2_VDO_MEAS_VS_COUNT_LO 		CBUS_REG_ADDR(VPP2_VDO_MEAS_VS_COUNT_LO)
#define P_GE2D_GEN_CTRL0 		CBUS_REG_ADDR(GE2D_GEN_CTRL0)
#define P_GE2D_GEN_CTRL1 		CBUS_REG_ADDR(GE2D_GEN_CTRL1)
#define P_GE2D_GEN_CTRL2 		CBUS_REG_ADDR(GE2D_GEN_CTRL2)
#define P_GE2D_CMD_CTRL 		CBUS_REG_ADDR(GE2D_CMD_CTRL)
#define P_GE2D_STATUS0 		CBUS_REG_ADDR(GE2D_STATUS0)
#define P_GE2D_STATUS1 		CBUS_REG_ADDR(GE2D_STATUS1)
#define P_GE2D_SRC1_DEF_COLOR 		CBUS_REG_ADDR(GE2D_SRC1_DEF_COLOR)
#define P_GE2D_SRC1_CLIPX_START_END 		CBUS_REG_ADDR(GE2D_SRC1_CLIPX_START_END)
#define P_GE2D_SRC1_CLIPY_START_END 		CBUS_REG_ADDR(GE2D_SRC1_CLIPY_START_END)
#define P_GE2D_SRC1_CANVAS 		CBUS_REG_ADDR(GE2D_SRC1_CANVAS)
#define P_GE2D_SRC1_X_START_END 		CBUS_REG_ADDR(GE2D_SRC1_X_START_END)
#define P_GE2D_SRC1_Y_START_END 		CBUS_REG_ADDR(GE2D_SRC1_Y_START_END)
#define P_GE2D_SRC1_LUT_ADDR 		CBUS_REG_ADDR(GE2D_SRC1_LUT_ADDR)
#define P_GE2D_SRC1_LUT_DAT 		CBUS_REG_ADDR(GE2D_SRC1_LUT_DAT)
#define P_GE2D_SRC1_FMT_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_FMT_CTRL)
#define P_GE2D_SRC2_DEF_COLOR 		CBUS_REG_ADDR(GE2D_SRC2_DEF_COLOR)
#define P_GE2D_SRC2_CLIPX_START_END 		CBUS_REG_ADDR(GE2D_SRC2_CLIPX_START_END)
#define P_GE2D_SRC2_CLIPY_START_END 		CBUS_REG_ADDR(GE2D_SRC2_CLIPY_START_END)
#define P_GE2D_SRC2_X_START_END 		CBUS_REG_ADDR(GE2D_SRC2_X_START_END)
#define P_GE2D_SRC2_Y_START_END 		CBUS_REG_ADDR(GE2D_SRC2_Y_START_END)
#define P_GE2D_DST_CLIPX_START_END 		CBUS_REG_ADDR(GE2D_DST_CLIPX_START_END)
#define P_GE2D_DST_CLIPY_START_END 		CBUS_REG_ADDR(GE2D_DST_CLIPY_START_END)
#define P_GE2D_DST_X_START_END 		CBUS_REG_ADDR(GE2D_DST_X_START_END)
#define P_GE2D_DST_Y_START_END 		CBUS_REG_ADDR(GE2D_DST_Y_START_END)
#define P_GE2D_SRC2_DST_CANVAS 		CBUS_REG_ADDR(GE2D_SRC2_DST_CANVAS)
#define P_GE2D_VSC_START_PHASE_STEP 		CBUS_REG_ADDR(GE2D_VSC_START_PHASE_STEP)
#define P_GE2D_VSC_PHASE_SLOPE 		CBUS_REG_ADDR(GE2D_VSC_PHASE_SLOPE)
#define P_GE2D_VSC_INI_CTRL 		CBUS_REG_ADDR(GE2D_VSC_INI_CTRL)
#define P_GE2D_HSC_START_PHASE_STEP 		CBUS_REG_ADDR(GE2D_HSC_START_PHASE_STEP)
#define P_GE2D_HSC_PHASE_SLOPE 		CBUS_REG_ADDR(GE2D_HSC_PHASE_SLOPE)
#define P_GE2D_HSC_INI_CTRL 		CBUS_REG_ADDR(GE2D_HSC_INI_CTRL)
#define P_GE2D_HSC_ADV_CTRL 		CBUS_REG_ADDR(GE2D_HSC_ADV_CTRL)
#define P_GE2D_SC_MISC_CTRL 		CBUS_REG_ADDR(GE2D_SC_MISC_CTRL)
#define P_GE2D_VSC_NRND_POINT 		CBUS_REG_ADDR(GE2D_VSC_NRND_POINT)
#define P_GE2D_VSC_NRND_PHASE 		CBUS_REG_ADDR(GE2D_VSC_NRND_PHASE)
#define P_GE2D_HSC_NRND_POINT 		CBUS_REG_ADDR(GE2D_HSC_NRND_POINT)
#define P_GE2D_HSC_NRND_PHASE 		CBUS_REG_ADDR(GE2D_HSC_NRND_PHASE)
#define P_GE2D_MATRIX_PRE_OFFSET 		CBUS_REG_ADDR(GE2D_MATRIX_PRE_OFFSET)
#define P_GE2D_MATRIX_COEF00_01 		CBUS_REG_ADDR(GE2D_MATRIX_COEF00_01)
#define P_GE2D_MATRIX_COEF02_10 		CBUS_REG_ADDR(GE2D_MATRIX_COEF02_10)
#define P_GE2D_MATRIX_COEF11_12 		CBUS_REG_ADDR(GE2D_MATRIX_COEF11_12)
#define P_GE2D_MATRIX_COEF20_21 		CBUS_REG_ADDR(GE2D_MATRIX_COEF20_21)
#define P_GE2D_MATRIX_COEF22_CTRL 		CBUS_REG_ADDR(GE2D_MATRIX_COEF22_CTRL)
#define P_GE2D_MATRIX_OFFSET 		CBUS_REG_ADDR(GE2D_MATRIX_OFFSET)
#define P_GE2D_ALU_OP_CTRL 		CBUS_REG_ADDR(GE2D_ALU_OP_CTRL)
#define P_GE2D_ALU_CONST_COLOR 		CBUS_REG_ADDR(GE2D_ALU_CONST_COLOR)
#define P_GE2D_SRC1_KEY 		CBUS_REG_ADDR(GE2D_SRC1_KEY)
#define P_GE2D_SRC1_KEY_MASK 		CBUS_REG_ADDR(GE2D_SRC1_KEY_MASK)
#define P_GE2D_SRC2_KEY 		CBUS_REG_ADDR(GE2D_SRC2_KEY)
#define P_GE2D_SRC2_KEY_MASK 		CBUS_REG_ADDR(GE2D_SRC2_KEY_MASK)
#define P_GE2D_DST_BITMASK 		CBUS_REG_ADDR(GE2D_DST_BITMASK)
#define P_GE2D_DP_ONOFF_CTRL 		CBUS_REG_ADDR(GE2D_DP_ONOFF_CTRL)
#define P_GE2D_SCALE_COEF_IDX 		CBUS_REG_ADDR(GE2D_SCALE_COEF_IDX)
#define P_GE2D_SCALE_COEF 		CBUS_REG_ADDR(GE2D_SCALE_COEF)
#define P_GE2D_SRC_OUTSIDE_ALPHA 		CBUS_REG_ADDR(GE2D_SRC_OUTSIDE_ALPHA)
#define P_GE2D_ANTIFLICK_CTRL0 		CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL0)
#define P_GE2D_ANTIFLICK_CTRL1 		CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL1)
#define P_GE2D_ANTIFLICK_COLOR_FILT0 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT0)
#define P_GE2D_ANTIFLICK_COLOR_FILT1 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT1)
#define P_GE2D_ANTIFLICK_COLOR_FILT2 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT2)
#define P_GE2D_ANTIFLICK_COLOR_FILT3 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT3)
#define P_GE2D_ANTIFLICK_ALPHA_FILT0 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT0)
#define P_GE2D_ANTIFLICK_ALPHA_FILT1 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT1)
#define P_GE2D_ANTIFLICK_ALPHA_FILT2 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT2)
#define P_GE2D_ANTIFLICK_ALPHA_FILT3 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT3)
#define P_GE2D_SRC1_RANGE_MAP_Y_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_Y_CTRL)
#define P_GE2D_SRC1_RANGE_MAP_CB_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CB_CTRL)
#define P_GE2D_SRC1_RANGE_MAP_CR_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CR_CTRL)
#define P_GE2D_ARB_BURST_NUM 		CBUS_REG_ADDR(GE2D_ARB_BURST_NUM)
#define P_GE2D_TID_TOKEN 		CBUS_REG_ADDR(GE2D_TID_TOKEN)
#define P_GE2D_GEN_CTRL3 		CBUS_REG_ADDR(GE2D_GEN_CTRL3)
#define P_GE2D_STATUS2 		CBUS_REG_ADDR(GE2D_STATUS2)
#define P_CSI2_CLK_RESET 		CBUS_REG_ADDR(CSI2_CLK_RESET)
#define P_CSI2_GEN_CTRL0 		CBUS_REG_ADDR(CSI2_GEN_CTRL0)
#define P_CSI2_FORCE_PIC_SIZE 		CBUS_REG_ADDR(CSI2_FORCE_PIC_SIZE)
#define P_CSI2_DDR_START_ADDR 		CBUS_REG_ADDR(CSI2_DDR_START_ADDR)
#define P_CSI2_DDR_END_ADDR 		CBUS_REG_ADDR(CSI2_DDR_END_ADDR)
#define P_CSI2_INTERRUPT_CTRL_STAT 		CBUS_REG_ADDR(CSI2_INTERRUPT_CTRL_STAT)
#define P_CSI2_PIC_SIZE_STAT 		CBUS_REG_ADDR(CSI2_PIC_SIZE_STAT)
#define P_CSI2_GEN_STAT0 		CBUS_REG_ADDR(CSI2_GEN_STAT0)
#define P_CSI2_DDR_WRPT_STAT 		CBUS_REG_ADDR(CSI2_DDR_WRPT_STAT)
#define P_CSI2_FS_EMBED_DDR_START 		CBUS_REG_ADDR(CSI2_FS_EMBED_DDR_START)
#define P_CSI2_FS_EMBED_DDR_END 		CBUS_REG_ADDR(CSI2_FS_EMBED_DDR_END)
#define P_CSI2_FE_EMBED_DDR_START 		CBUS_REG_ADDR(CSI2_FE_EMBED_DDR_START)
#define P_CSI2_FE_EMBED_DDR_END 		CBUS_REG_ADDR(CSI2_FE_EMBED_DDR_END)
#define P_CSI2_MEM_PIXEL_BYTE_CNT 		CBUS_REG_ADDR(CSI2_MEM_PIXEL_BYTE_CNT)
#define P_CSI2_MEM_PIXEL_LINE_CNT 		CBUS_REG_ADDR(CSI2_MEM_PIXEL_LINE_CNT)
#define P_CSI2_PIXEL_DDR_START 		CBUS_REG_ADDR(CSI2_PIXEL_DDR_START)
#define P_CSI2_PIXEL_DDR_END 		CBUS_REG_ADDR(CSI2_PIXEL_DDR_END)
#define P_CSI2_USER_DDR_START 		CBUS_REG_ADDR(CSI2_USER_DDR_START)
#define P_CSI2_USER_DDR_END 		CBUS_REG_ADDR(CSI2_USER_DDR_END)
#define P_CSI2_DATA_TYPE_IN_MEM 		CBUS_REG_ADDR(CSI2_DATA_TYPE_IN_MEM)
#define P_CSI2_ERR_STAT0 		CBUS_REG_ADDR(CSI2_ERR_STAT0)
#define P_VIU_ADDR_START 		CBUS_REG_ADDR(VIU_ADDR_START)
#define P_VIU_ADDR_END 		CBUS_REG_ADDR(VIU_ADDR_END)
#define P_TRACE_REG 		CBUS_REG_ADDR(TRACE_REG)
#define P_VIU_SW_RESET 		CBUS_REG_ADDR(VIU_SW_RESET)
#define P_VIU_OSD1_CTRL_STAT 		CBUS_REG_ADDR(VIU_OSD1_CTRL_STAT)
#define P_VIU_OSD1_CTRL_STAT2 		CBUS_REG_ADDR(VIU_OSD1_CTRL_STAT2)
#define P_VIU_OSD1_COLOR_ADDR 		CBUS_REG_ADDR(VIU_OSD1_COLOR_ADDR)
#define P_VIU_OSD1_COLOR 		CBUS_REG_ADDR(VIU_OSD1_COLOR)
#define P_VIU_OSD1_TCOLOR_AG0 		CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG0)
#define P_VIU_OSD1_TCOLOR_AG1 		CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG1)
#define P_VIU_OSD1_TCOLOR_AG2 		CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG2)
#define P_VIU_OSD1_TCOLOR_AG3 		CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG3)
#define P_VIU_OSD1_BLK0_CFG_W0 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W0)
#define P_VIU_OSD1_BLK1_CFG_W0 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W0)
#define P_VIU_OSD1_BLK2_CFG_W0 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W0)
#define P_VIU_OSD1_BLK3_CFG_W0 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W0)
#define P_VIU_OSD1_BLK0_CFG_W1 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W1)
#define P_VIU_OSD1_BLK1_CFG_W1 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W1)
#define P_VIU_OSD1_BLK2_CFG_W1 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W1)
#define P_VIU_OSD1_BLK3_CFG_W1 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W1)
#define P_VIU_OSD1_BLK0_CFG_W2 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W2)
#define P_VIU_OSD1_BLK1_CFG_W2 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W2)
#define P_VIU_OSD1_BLK2_CFG_W2 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W2)
#define P_VIU_OSD1_BLK3_CFG_W2 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W2)
#define P_VIU_OSD1_BLK0_CFG_W3 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W3)
#define P_VIU_OSD1_BLK1_CFG_W3 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W3)
#define P_VIU_OSD1_BLK2_CFG_W3 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W3)
#define P_VIU_OSD1_BLK3_CFG_W3 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W3)
#define P_VIU_OSD1_BLK0_CFG_W4 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W4)
#define P_VIU_OSD1_BLK1_CFG_W4 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W4)
#define P_VIU_OSD1_BLK2_CFG_W4 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W4)
#define P_VIU_OSD1_BLK3_CFG_W4 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W4)
#define P_VIU_OSD1_FIFO_CTRL_STAT 		CBUS_REG_ADDR(VIU_OSD1_FIFO_CTRL_STAT)
#define P_VIU_OSD1_TEST_RDDATA 		CBUS_REG_ADDR(VIU_OSD1_TEST_RDDATA)
#define P_VIU_OSD2_CTRL_STAT 		CBUS_REG_ADDR(VIU_OSD2_CTRL_STAT)
#define P_VIU_OSD2_CTRL_STAT2 		CBUS_REG_ADDR(VIU_OSD2_CTRL_STAT2)
#define P_VIU_OSD2_COLOR_ADDR 		CBUS_REG_ADDR(VIU_OSD2_COLOR_ADDR)
#define P_VIU_OSD2_COLOR 		CBUS_REG_ADDR(VIU_OSD2_COLOR)
#define P_VIU_OSD2_HL1_H_START_END 		CBUS_REG_ADDR(VIU_OSD2_HL1_H_START_END)
#define P_VIU_OSD2_HL1_V_START_END 		CBUS_REG_ADDR(VIU_OSD2_HL1_V_START_END)
#define P_VIU_OSD2_HL2_H_START_END 		CBUS_REG_ADDR(VIU_OSD2_HL2_H_START_END)
#define P_VIU_OSD2_HL2_V_START_END 		CBUS_REG_ADDR(VIU_OSD2_HL2_V_START_END)
#define P_VIU_OSD2_TCOLOR_AG0 		CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG0)
#define P_VIU_OSD2_TCOLOR_AG1 		CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG1)
#define P_VIU_OSD2_TCOLOR_AG2 		CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG2)
#define P_VIU_OSD2_TCOLOR_AG3 		CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG3)
#define P_VIU_OSD2_BLK0_CFG_W0 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W0)
#define P_VIU_OSD2_BLK1_CFG_W0 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W0)
#define P_VIU_OSD2_BLK2_CFG_W0 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W0)
#define P_VIU_OSD2_BLK3_CFG_W0 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W0)
#define P_VIU_OSD2_BLK0_CFG_W1 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W1)
#define P_VIU_OSD2_BLK1_CFG_W1 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W1)
#define P_VIU_OSD2_BLK2_CFG_W1 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W1)
#define P_VIU_OSD2_BLK3_CFG_W1 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W1)
#define P_VIU_OSD2_BLK0_CFG_W2 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W2)
#define P_VIU_OSD2_BLK1_CFG_W2 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W2)
#define P_VIU_OSD2_BLK2_CFG_W2 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W2)
#define P_VIU_OSD2_BLK3_CFG_W2 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W2)
#define P_VIU_OSD2_BLK0_CFG_W3 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W3)
#define P_VIU_OSD2_BLK1_CFG_W3 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W3)
#define P_VIU_OSD2_BLK2_CFG_W3 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W3)
#define P_VIU_OSD2_BLK3_CFG_W3 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W3)
#define P_VIU_OSD2_BLK0_CFG_W4 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W4)
#define P_VIU_OSD2_BLK1_CFG_W4 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W4)
#define P_VIU_OSD2_BLK2_CFG_W4 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W4)
#define P_VIU_OSD2_BLK3_CFG_W4 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W4)
#define P_VIU_OSD2_FIFO_CTRL_STAT 		CBUS_REG_ADDR(VIU_OSD2_FIFO_CTRL_STAT)
#define P_VIU_OSD2_TEST_RDDATA 		CBUS_REG_ADDR(VIU_OSD2_TEST_RDDATA)
#define P_VD1_IF0_GEN_REG 		CBUS_REG_ADDR(VD1_IF0_GEN_REG)
#define P_VD1_IF0_CANVAS0 		CBUS_REG_ADDR(VD1_IF0_CANVAS0)
#define P_VD1_IF0_CANVAS1 		CBUS_REG_ADDR(VD1_IF0_CANVAS1)
#define P_VD1_IF0_LUMA_X0 		CBUS_REG_ADDR(VD1_IF0_LUMA_X0)
#define P_VD1_IF0_LUMA_Y0 		CBUS_REG_ADDR(VD1_IF0_LUMA_Y0)
#define P_VD1_IF0_CHROMA_X0 		CBUS_REG_ADDR(VD1_IF0_CHROMA_X0)
#define P_VD1_IF0_CHROMA_Y0 		CBUS_REG_ADDR(VD1_IF0_CHROMA_Y0)
#define P_VD1_IF0_LUMA_X1 		CBUS_REG_ADDR(VD1_IF0_LUMA_X1)
#define P_VD1_IF0_LUMA_Y1 		CBUS_REG_ADDR(VD1_IF0_LUMA_Y1)
#define P_VD1_IF0_CHROMA_X1 		CBUS_REG_ADDR(VD1_IF0_CHROMA_X1)
#define P_VD1_IF0_CHROMA_Y1 		CBUS_REG_ADDR(VD1_IF0_CHROMA_Y1)
#define P_VD1_IF0_RPT_LOOP 		CBUS_REG_ADDR(VD1_IF0_RPT_LOOP)
#define P_VD1_IF0_LUMA0_RPT_PAT 		CBUS_REG_ADDR(VD1_IF0_LUMA0_RPT_PAT)
#define P_VD1_IF0_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(VD1_IF0_CHROMA0_RPT_PAT)
#define P_VD1_IF0_LUMA1_RPT_PAT 		CBUS_REG_ADDR(VD1_IF0_LUMA1_RPT_PAT)
#define P_VD1_IF0_CHROMA1_RPT_PAT 		CBUS_REG_ADDR(VD1_IF0_CHROMA1_RPT_PAT)
#define P_VD1_IF0_LUMA_PSEL 		CBUS_REG_ADDR(VD1_IF0_LUMA_PSEL)
#define P_VD1_IF0_CHROMA_PSEL 		CBUS_REG_ADDR(VD1_IF0_CHROMA_PSEL)
#define P_VD1_IF0_DUMMY_PIXEL 		CBUS_REG_ADDR(VD1_IF0_DUMMY_PIXEL)
#define P_VD1_IF0_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(VD1_IF0_LUMA_FIFO_SIZE)
#define P_VD1_IF0_RANGE_MAP_Y 		CBUS_REG_ADDR(VD1_IF0_RANGE_MAP_Y)
#define P_VD1_IF0_RANGE_MAP_CB 		CBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CB)
#define P_VD1_IF0_RANGE_MAP_CR 		CBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CR)
#define P_VD1_IF0_GEN_REG2 		CBUS_REG_ADDR(VD1_IF0_GEN_REG2)
#define P_VIU_VD1_FMT_CTRL 		CBUS_REG_ADDR(VIU_VD1_FMT_CTRL)
#define P_VIU_VD1_FMT_W 		CBUS_REG_ADDR(VIU_VD1_FMT_W)
#define P_VD2_IF0_GEN_REG 		CBUS_REG_ADDR(VD2_IF0_GEN_REG)
#define P_VD2_IF0_CANVAS0 		CBUS_REG_ADDR(VD2_IF0_CANVAS0)
#define P_VD2_IF0_CANVAS1 		CBUS_REG_ADDR(VD2_IF0_CANVAS1)
#define P_VD2_IF0_LUMA_X0 		CBUS_REG_ADDR(VD2_IF0_LUMA_X0)
#define P_VD2_IF0_LUMA_Y0 		CBUS_REG_ADDR(VD2_IF0_LUMA_Y0)
#define P_VD2_IF0_CHROMA_X0 		CBUS_REG_ADDR(VD2_IF0_CHROMA_X0)
#define P_VD2_IF0_CHROMA_Y0 		CBUS_REG_ADDR(VD2_IF0_CHROMA_Y0)
#define P_VD2_IF0_LUMA_X1 		CBUS_REG_ADDR(VD2_IF0_LUMA_X1)
#define P_VD2_IF0_LUMA_Y1 		CBUS_REG_ADDR(VD2_IF0_LUMA_Y1)
#define P_VD2_IF0_CHROMA_X1 		CBUS_REG_ADDR(VD2_IF0_CHROMA_X1)
#define P_VD2_IF0_CHROMA_Y1 		CBUS_REG_ADDR(VD2_IF0_CHROMA_Y1)
#define P_VD2_IF0_RPT_LOOP 		CBUS_REG_ADDR(VD2_IF0_RPT_LOOP)
#define P_VD2_IF0_LUMA0_RPT_PAT 		CBUS_REG_ADDR(VD2_IF0_LUMA0_RPT_PAT)
#define P_VD2_IF0_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(VD2_IF0_CHROMA0_RPT_PAT)
#define P_VD2_IF0_LUMA1_RPT_PAT 		CBUS_REG_ADDR(VD2_IF0_LUMA1_RPT_PAT)
#define P_VD2_IF0_CHROMA1_RPT_PAT 		CBUS_REG_ADDR(VD2_IF0_CHROMA1_RPT_PAT)
#define P_VD2_IF0_LUMA_PSEL 		CBUS_REG_ADDR(VD2_IF0_LUMA_PSEL)
#define P_VD2_IF0_CHROMA_PSEL 		CBUS_REG_ADDR(VD2_IF0_CHROMA_PSEL)
#define P_VD2_IF0_DUMMY_PIXEL 		CBUS_REG_ADDR(VD2_IF0_DUMMY_PIXEL)
#define P_VD2_IF0_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(VD2_IF0_LUMA_FIFO_SIZE)
#define P_VD2_IF0_RANGE_MAP_Y 		CBUS_REG_ADDR(VD2_IF0_RANGE_MAP_Y)
#define P_VD2_IF0_RANGE_MAP_CB 		CBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CB)
#define P_VD2_IF0_RANGE_MAP_CR 		CBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CR)
#define P_VD2_IF0_GEN_REG2 		CBUS_REG_ADDR(VD2_IF0_GEN_REG2)
#define P_VIU_VD2_FMT_CTRL 		CBUS_REG_ADDR(VIU_VD2_FMT_CTRL)
#define P_VIU_VD2_FMT_W 		CBUS_REG_ADDR(VIU_VD2_FMT_W)
#define P_DI_PRE_CTRL 		CBUS_REG_ADDR(DI_PRE_CTRL)
#define P_DI_POST_CTRL 		CBUS_REG_ADDR(DI_POST_CTRL)
#define P_DI_POST_SIZE 		CBUS_REG_ADDR(DI_POST_SIZE)
#define P_DI_PRE_SIZE 		CBUS_REG_ADDR(DI_PRE_SIZE)
#define P_DI_EI_CTRL0 		CBUS_REG_ADDR(DI_EI_CTRL0)
#define P_DI_EI_CTRL1 		CBUS_REG_ADDR(DI_EI_CTRL1)
#define P_DI_EI_CTRL2 		CBUS_REG_ADDR(DI_EI_CTRL2)
#define P_DI_NR_CTRL0 		CBUS_REG_ADDR(DI_NR_CTRL0)
#define P_DI_NR_CTRL1 		CBUS_REG_ADDR(DI_NR_CTRL1)
#define P_DI_NR_CTRL2 		CBUS_REG_ADDR(DI_NR_CTRL2)
#define P_DI_NR_CTRL3 		CBUS_REG_ADDR(DI_NR_CTRL3)
#define P_DI_MTN_CTRL 		CBUS_REG_ADDR(DI_MTN_CTRL)
#define P_DI_MTN_CTRL1 		CBUS_REG_ADDR(DI_MTN_CTRL1)
#define P_DI_BLEND_CTRL 		CBUS_REG_ADDR(DI_BLEND_CTRL)
#define P_DI_BLEND_CTRL1 		CBUS_REG_ADDR(DI_BLEND_CTRL1)
#define P_DI_BLEND_CTRL2 		CBUS_REG_ADDR(DI_BLEND_CTRL2)
#define P_DI_BLEND_REG0_X 		CBUS_REG_ADDR(DI_BLEND_REG0_X)
#define P_DI_BLEND_REG0_Y 		CBUS_REG_ADDR(DI_BLEND_REG0_Y)
#define P_DI_BLEND_REG1_X 		CBUS_REG_ADDR(DI_BLEND_REG1_X)
#define P_DI_BLEND_REG1_Y 		CBUS_REG_ADDR(DI_BLEND_REG1_Y)
#define P_DI_BLEND_REG2_X 		CBUS_REG_ADDR(DI_BLEND_REG2_X)
#define P_DI_BLEND_REG2_Y 		CBUS_REG_ADDR(DI_BLEND_REG2_Y)
#define P_DI_BLEND_REG3_X 		CBUS_REG_ADDR(DI_BLEND_REG3_X)
#define P_DI_BLEND_REG3_Y 		CBUS_REG_ADDR(DI_BLEND_REG3_Y)
#define P_DI_CLKG_CTRL 		CBUS_REG_ADDR(DI_CLKG_CTRL)
#define P_DI_MC_REG0_X 		CBUS_REG_ADDR(DI_MC_REG0_X)
#define P_DI_MC_REG0_Y 		CBUS_REG_ADDR(DI_MC_REG0_Y)
#define P_DI_MC_REG1_X 		CBUS_REG_ADDR(DI_MC_REG1_X)
#define P_DI_MC_REG1_Y 		CBUS_REG_ADDR(DI_MC_REG1_Y)
#define P_DI_MC_REG2_X 		CBUS_REG_ADDR(DI_MC_REG2_X)
#define P_DI_MC_REG2_Y 		CBUS_REG_ADDR(DI_MC_REG2_Y)
#define P_DI_MC_REG3_X 		CBUS_REG_ADDR(DI_MC_REG3_X)
#define P_DI_MC_REG3_Y 		CBUS_REG_ADDR(DI_MC_REG3_Y)
#define P_DI_MC_REG4_X 		CBUS_REG_ADDR(DI_MC_REG4_X)
#define P_DI_MC_REG4_Y 		CBUS_REG_ADDR(DI_MC_REG4_Y)
#define P_DI_MC_32LVL0 		CBUS_REG_ADDR(DI_MC_32LVL0)
#define P_DI_MC_32LVL1 		CBUS_REG_ADDR(DI_MC_32LVL1)
#define P_DI_MC_22LVL0 		CBUS_REG_ADDR(DI_MC_22LVL0)
#define P_DI_MC_22LVL1 		CBUS_REG_ADDR(DI_MC_22LVL1)
#define P_DI_MC_22LVL2 		CBUS_REG_ADDR(DI_MC_22LVL2)
#define P_DI_MC_CTRL 		CBUS_REG_ADDR(DI_MC_CTRL)
#define P_DI_INTR_CTRL 		CBUS_REG_ADDR(DI_INTR_CTRL)
#define P_DI_INFO_ADDR 		CBUS_REG_ADDR(DI_INFO_ADDR)
#define P_DI_INFO_DATA 		CBUS_REG_ADDR(DI_INFO_DATA)
#define P_DI_PRE_HOLD 		CBUS_REG_ADDR(DI_PRE_HOLD)
#define P_DI_NRWR_X 		CBUS_REG_ADDR(DI_NRWR_X)
#define P_DI_NRWR_Y 		CBUS_REG_ADDR(DI_NRWR_Y)
#define P_DI_NRWR_CTRL 		CBUS_REG_ADDR(DI_NRWR_CTRL)
#define P_DI_MTNWR_X 		CBUS_REG_ADDR(DI_MTNWR_X)
#define P_DI_MTNWR_Y 		CBUS_REG_ADDR(DI_MTNWR_Y)
#define P_DI_MTNWR_CTRL 		CBUS_REG_ADDR(DI_MTNWR_CTRL)
#define P_DI_DIWR_X 		CBUS_REG_ADDR(DI_DIWR_X)
#define P_DI_DIWR_Y 		CBUS_REG_ADDR(DI_DIWR_Y)
#define P_DI_DIWR_CTRL 		CBUS_REG_ADDR(DI_DIWR_CTRL)
#define P_DI_MTNCRD_X 		CBUS_REG_ADDR(DI_MTNCRD_X)
#define P_DI_MTNCRD_Y 		CBUS_REG_ADDR(DI_MTNCRD_Y)
#define P_DI_MTNPRD_X 		CBUS_REG_ADDR(DI_MTNPRD_X)
#define P_DI_MTNPRD_Y 		CBUS_REG_ADDR(DI_MTNPRD_Y)
#define P_DI_MTNRD_CTRL 		CBUS_REG_ADDR(DI_MTNRD_CTRL)
#define P_DI_INP_GEN_REG 		CBUS_REG_ADDR(DI_INP_GEN_REG)
#define P_DI_INP_CANVAS0 		CBUS_REG_ADDR(DI_INP_CANVAS0)
#define P_DI_INP_LUMA_X0 		CBUS_REG_ADDR(DI_INP_LUMA_X0)
#define P_DI_INP_LUMA_Y0 		CBUS_REG_ADDR(DI_INP_LUMA_Y0)
#define P_DI_INP_CHROMA_X0 		CBUS_REG_ADDR(DI_INP_CHROMA_X0)
#define P_DI_INP_CHROMA_Y0 		CBUS_REG_ADDR(DI_INP_CHROMA_Y0)
#define P_DI_INP_RPT_LOOP 		CBUS_REG_ADDR(DI_INP_RPT_LOOP)
#define P_DI_INP_LUMA0_RPT_PAT 		CBUS_REG_ADDR(DI_INP_LUMA0_RPT_PAT)
#define P_DI_INP_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(DI_INP_CHROMA0_RPT_PAT)
#define P_DI_INP_DUMMY_PIXEL 		CBUS_REG_ADDR(DI_INP_DUMMY_PIXEL)
#define P_DI_INP_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(DI_INP_LUMA_FIFO_SIZE)
#define P_DI_INP_RANGE_MAP_Y 		CBUS_REG_ADDR(DI_INP_RANGE_MAP_Y)
#define P_DI_INP_RANGE_MAP_CB 		CBUS_REG_ADDR(DI_INP_RANGE_MAP_CB)
#define P_DI_INP_RANGE_MAP_CR 		CBUS_REG_ADDR(DI_INP_RANGE_MAP_CR)
#define P_DI_INP_GEN_REG2 		CBUS_REG_ADDR(DI_INP_GEN_REG2)
#define P_DI_INP_FMT_CTRL 		CBUS_REG_ADDR(DI_INP_FMT_CTRL)
#define P_DI_INP_FMT_W 		CBUS_REG_ADDR(DI_INP_FMT_W)
#define P_DI_MEM_GEN_REG 		CBUS_REG_ADDR(DI_MEM_GEN_REG)
#define P_DI_MEM_CANVAS0 		CBUS_REG_ADDR(DI_MEM_CANVAS0)
#define P_DI_MEM_LUMA_X0 		CBUS_REG_ADDR(DI_MEM_LUMA_X0)
#define P_DI_MEM_LUMA_Y0 		CBUS_REG_ADDR(DI_MEM_LUMA_Y0)
#define P_DI_MEM_CHROMA_X0 		CBUS_REG_ADDR(DI_MEM_CHROMA_X0)
#define P_DI_MEM_CHROMA_Y0 		CBUS_REG_ADDR(DI_MEM_CHROMA_Y0)
#define P_DI_MEM_RPT_LOOP 		CBUS_REG_ADDR(DI_MEM_RPT_LOOP)
#define P_DI_MEM_LUMA0_RPT_PAT 		CBUS_REG_ADDR(DI_MEM_LUMA0_RPT_PAT)
#define P_DI_MEM_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(DI_MEM_CHROMA0_RPT_PAT)
#define P_DI_MEM_DUMMY_PIXEL 		CBUS_REG_ADDR(DI_MEM_DUMMY_PIXEL)
#define P_DI_MEM_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(DI_MEM_LUMA_FIFO_SIZE)
#define P_DI_MEM_RANGE_MAP_Y 		CBUS_REG_ADDR(DI_MEM_RANGE_MAP_Y)
#define P_DI_MEM_RANGE_MAP_CB 		CBUS_REG_ADDR(DI_MEM_RANGE_MAP_CB)
#define P_DI_MEM_RANGE_MAP_CR 		CBUS_REG_ADDR(DI_MEM_RANGE_MAP_CR)
#define P_DI_MEM_GEN_REG2 		CBUS_REG_ADDR(DI_MEM_GEN_REG2)
#define P_DI_MEM_FMT_CTRL 		CBUS_REG_ADDR(DI_MEM_FMT_CTRL)
#define P_DI_MEM_FMT_W 		CBUS_REG_ADDR(DI_MEM_FMT_W)
#define P_DI_IF1_GEN_REG 		CBUS_REG_ADDR(DI_IF1_GEN_REG)
#define P_DI_IF1_CANVAS0 		CBUS_REG_ADDR(DI_IF1_CANVAS0)
#define P_DI_IF1_LUMA_X0 		CBUS_REG_ADDR(DI_IF1_LUMA_X0)
#define P_DI_IF1_LUMA_Y0 		CBUS_REG_ADDR(DI_IF1_LUMA_Y0)
#define P_DI_IF1_CHROMA_X0 		CBUS_REG_ADDR(DI_IF1_CHROMA_X0)
#define P_DI_IF1_CHROMA_Y0 		CBUS_REG_ADDR(DI_IF1_CHROMA_Y0)
#define P_DI_IF1_RPT_LOOP 		CBUS_REG_ADDR(DI_IF1_RPT_LOOP)
#define P_DI_IF1_LUMA0_RPT_PAT 		CBUS_REG_ADDR(DI_IF1_LUMA0_RPT_PAT)
#define P_DI_IF1_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(DI_IF1_CHROMA0_RPT_PAT)
#define P_DI_IF1_DUMMY_PIXEL 		CBUS_REG_ADDR(DI_IF1_DUMMY_PIXEL)
#define P_DI_IF1_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(DI_IF1_LUMA_FIFO_SIZE)
#define P_DI_IF1_RANGE_MAP_Y 		CBUS_REG_ADDR(DI_IF1_RANGE_MAP_Y)
#define P_DI_IF1_RANGE_MAP_CB 		CBUS_REG_ADDR(DI_IF1_RANGE_MAP_CB)
#define P_DI_IF1_RANGE_MAP_CR 		CBUS_REG_ADDR(DI_IF1_RANGE_MAP_CR)
#define P_DI_IF1_GEN_REG2 		CBUS_REG_ADDR(DI_IF1_GEN_REG2)
#define P_DI_IF1_FMT_CTRL 		CBUS_REG_ADDR(DI_IF1_FMT_CTRL)
#define P_DI_IF1_FMT_W 		CBUS_REG_ADDR(DI_IF1_FMT_W)
#define P_DI_CHAN2_GEN_REG 		CBUS_REG_ADDR(DI_CHAN2_GEN_REG)
#define P_DI_CHAN2_CANVAS 		CBUS_REG_ADDR(DI_CHAN2_CANVAS)
#define P_DI_CHAN2_LUMA_X 		CBUS_REG_ADDR(DI_CHAN2_LUMA_X)
#define P_DI_CHAN2_LUMA_Y 		CBUS_REG_ADDR(DI_CHAN2_LUMA_Y)
#define P_DI_CHAN2_RPT_LOOP 		CBUS_REG_ADDR(DI_CHAN2_RPT_LOOP)
#define P_DI_CHAN2_LUMA_RPT_PAT 		CBUS_REG_ADDR(DI_CHAN2_LUMA_RPT_PAT)
#define P_DI_CHAN2_DUMMY_PIXEL 		CBUS_REG_ADDR(DI_CHAN2_DUMMY_PIXEL)
#define P_DI_CHAN2_RANGE_MAP_Y 		CBUS_REG_ADDR(DI_CHAN2_RANGE_MAP_Y)
#define P_VIU2_ADDR_START 		CBUS_REG_ADDR(VIU2_ADDR_START)
#define P_VIU2_ADDR_END 		CBUS_REG_ADDR(VIU2_ADDR_END)
#define P_VIU2_OSD1_CTRL_STAT 		CBUS_REG_ADDR(VIU2_OSD1_CTRL_STAT)
#define P_VIU2_OSD1_CTRL_STAT2 		CBUS_REG_ADDR(VIU2_OSD1_CTRL_STAT2)
#define P_VIU2_OSD1_COLOR_ADDR 		CBUS_REG_ADDR(VIU2_OSD1_COLOR_ADDR)
#define P_VIU2_OSD1_COLOR 		CBUS_REG_ADDR(VIU2_OSD1_COLOR)
#define P_VIU2_OSD1_TCOLOR_AG0 		CBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG0)
#define P_VIU2_OSD1_TCOLOR_AG1 		CBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG1)
#define P_VIU2_OSD1_TCOLOR_AG2 		CBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG2)
#define P_VIU2_OSD1_TCOLOR_AG3 		CBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG3)
#define P_VIU2_OSD1_BLK0_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W0)
#define P_VIU2_OSD1_BLK1_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W0)
#define P_VIU2_OSD1_BLK2_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W0)
#define P_VIU2_OSD1_BLK3_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W0)
#define P_VIU2_OSD1_BLK0_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W1)
#define P_VIU2_OSD1_BLK1_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W1)
#define P_VIU2_OSD1_BLK2_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W1)
#define P_VIU2_OSD1_BLK3_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W1)
#define P_VIU2_OSD1_BLK0_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W2)
#define P_VIU2_OSD1_BLK1_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W2)
#define P_VIU2_OSD1_BLK2_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W2)
#define P_VIU2_OSD1_BLK3_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W2)
#define P_VIU2_OSD1_BLK0_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W3)
#define P_VIU2_OSD1_BLK1_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W3)
#define P_VIU2_OSD1_BLK2_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W3)
#define P_VIU2_OSD1_BLK3_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W3)
#define P_VIU2_OSD1_BLK0_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W4)
#define P_VIU2_OSD1_BLK1_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W4)
#define P_VIU2_OSD1_BLK2_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W4)
#define P_VIU2_OSD1_BLK3_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W4)
#define P_VIU2_OSD1_FIFO_CTRL_STAT 		CBUS_REG_ADDR(VIU2_OSD1_FIFO_CTRL_STAT)
#define P_VIU2_OSD1_TEST_RDDATA 		CBUS_REG_ADDR(VIU2_OSD1_TEST_RDDATA)
#define P_VIU2_OSD2_CTRL_STAT 		CBUS_REG_ADDR(VIU2_OSD2_CTRL_STAT)
#define P_VIU2_OSD2_CTRL_STAT2 		CBUS_REG_ADDR(VIU2_OSD2_CTRL_STAT2)
#define P_VIU2_OSD2_COLOR_ADDR 		CBUS_REG_ADDR(VIU2_OSD2_COLOR_ADDR)
#define P_VIU2_OSD2_COLOR 		CBUS_REG_ADDR(VIU2_OSD2_COLOR)
#define P_VIU2_OSD2_HL1_H_START_END 		CBUS_REG_ADDR(VIU2_OSD2_HL1_H_START_END)
#define P_VIU2_OSD2_HL1_V_START_END 		CBUS_REG_ADDR(VIU2_OSD2_HL1_V_START_END)
#define P_VIU2_OSD2_HL2_H_START_END 		CBUS_REG_ADDR(VIU2_OSD2_HL2_H_START_END)
#define P_VIU2_OSD2_HL2_V_START_END 		CBUS_REG_ADDR(VIU2_OSD2_HL2_V_START_END)
#define P_VIU2_OSD2_TCOLOR_AG0 		CBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG0)
#define P_VIU2_OSD2_TCOLOR_AG1 		CBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG1)
#define P_VIU2_OSD2_TCOLOR_AG2 		CBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG2)
#define P_VIU2_OSD2_TCOLOR_AG3 		CBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG3)
#define P_VIU2_OSD2_BLK0_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W0)
#define P_VIU2_OSD2_BLK1_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W0)
#define P_VIU2_OSD2_BLK2_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W0)
#define P_VIU2_OSD2_BLK3_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W0)
#define P_VIU2_OSD2_BLK0_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W1)
#define P_VIU2_OSD2_BLK1_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W1)
#define P_VIU2_OSD2_BLK2_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W1)
#define P_VIU2_OSD2_BLK3_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W1)
#define P_VIU2_OSD2_BLK0_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W2)
#define P_VIU2_OSD2_BLK1_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W2)
#define P_VIU2_OSD2_BLK2_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W2)
#define P_VIU2_OSD2_BLK3_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W2)
#define P_VIU2_OSD2_BLK0_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W3)
#define P_VIU2_OSD2_BLK1_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W3)
#define P_VIU2_OSD2_BLK2_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W3)
#define P_VIU2_OSD2_BLK3_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W3)
#define P_VIU2_OSD2_BLK0_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W4)
#define P_VIU2_OSD2_BLK1_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W4)
#define P_VIU2_OSD2_BLK2_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W4)
#define P_VIU2_OSD2_BLK3_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W4)
#define P_VIU2_OSD2_FIFO_CTRL_STAT 		CBUS_REG_ADDR(VIU2_OSD2_FIFO_CTRL_STAT)
#define P_VIU2_OSD2_TEST_RDDATA 		CBUS_REG_ADDR(VIU2_OSD2_TEST_RDDATA)
#define P_VIU2_VD1_IF0_GEN_REG 		CBUS_REG_ADDR(VIU2_VD1_IF0_GEN_REG)
#define P_VIU2_VD1_IF0_CANVAS0 		CBUS_REG_ADDR(VIU2_VD1_IF0_CANVAS0)
#define P_VIU2_VD1_IF0_CANVAS1 		CBUS_REG_ADDR(VIU2_VD1_IF0_CANVAS1)
#define P_VIU2_VD1_IF0_LUMA_X0 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_X0)
#define P_VIU2_VD1_IF0_LUMA_Y0 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_Y0)
#define P_VIU2_VD1_IF0_CHROMA_X0 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_X0)
#define P_VIU2_VD1_IF0_CHROMA_Y0 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_Y0)
#define P_VIU2_VD1_IF0_LUMA_X1 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_X1)
#define P_VIU2_VD1_IF0_LUMA_Y1 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_Y1)
#define P_VIU2_VD1_IF0_CHROMA_X1 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_X1)
#define P_VIU2_VD1_IF0_CHROMA_Y1 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_Y1)
#define P_VIU2_VD1_IF0_RPT_LOOP 		CBUS_REG_ADDR(VIU2_VD1_IF0_RPT_LOOP)
#define P_VIU2_VD1_IF0_LUMA0_RPT_PAT 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA0_RPT_PAT)
#define P_VIU2_VD1_IF0_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA0_RPT_PAT)
#define P_VIU2_VD1_IF0_LUMA1_RPT_PAT 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA1_RPT_PAT)
#define P_VIU2_VD1_IF0_CHROMA1_RPT_PAT 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA1_RPT_PAT)
#define P_VIU2_VD1_IF0_LUMA_PSEL 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_PSEL)
#define P_VIU2_VD1_IF0_CHROMA_PSEL 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_PSEL)
#define P_VIU2_VD1_IF0_DUMMY_PIXEL 		CBUS_REG_ADDR(VIU2_VD1_IF0_DUMMY_PIXEL)
#define P_VIU2_VD1_IF0_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_FIFO_SIZE)
#define P_VIU2_VD1_IF0_RANGE_MAP_Y 		CBUS_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_Y)
#define P_VIU2_VD1_IF0_RANGE_MAP_CB 		CBUS_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_CB)
#define P_VIU2_VD1_IF0_RANGE_MAP_CR 		CBUS_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_CR)
#define P_VIU2_VD1_IF0_GEN_REG2 		CBUS_REG_ADDR(VIU2_VD1_IF0_GEN_REG2)
#define P_VIU2_VD1_FMT_CTRL 		CBUS_REG_ADDR(VIU2_VD1_FMT_CTRL)
#define P_VIU2_VD1_FMT_W 		CBUS_REG_ADDR(VIU2_VD1_FMT_W)
#define P_ENCP_VFIFO2VD_CTL 		CBUS_REG_ADDR(ENCP_VFIFO2VD_CTL)
#define P_ENCP_VFIFO2VD_PIXEL_START 		CBUS_REG_ADDR(ENCP_VFIFO2VD_PIXEL_START)
#define P_ENCP_VFIFO2VD_PIXEL_END 		CBUS_REG_ADDR(ENCP_VFIFO2VD_PIXEL_END)
#define P_ENCP_VFIFO2VD_LINE_TOP_START 		CBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_TOP_START)
#define P_ENCP_VFIFO2VD_LINE_TOP_END 		CBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_TOP_END)
#define P_ENCP_VFIFO2VD_LINE_BOT_START 		CBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_BOT_START)
#define P_ENCP_VFIFO2VD_LINE_BOT_END 		CBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_BOT_END)
#define P_VENC_SYNC_ROUTE 		CBUS_REG_ADDR(VENC_SYNC_ROUTE)
#define P_VENC_VIDEO_EXSRC 		CBUS_REG_ADDR(VENC_VIDEO_EXSRC)
#define P_VENC_DVI_SETTING 		CBUS_REG_ADDR(VENC_DVI_SETTING)
#define P_VENC_C656_CTRL 		CBUS_REG_ADDR(VENC_C656_CTRL)
#define P_VENC_UPSAMPLE_CTRL0 		CBUS_REG_ADDR(VENC_UPSAMPLE_CTRL0)
#define P_VENC_UPSAMPLE_CTRL1 		CBUS_REG_ADDR(VENC_UPSAMPLE_CTRL1)
#define P_VENC_UPSAMPLE_CTRL2 		CBUS_REG_ADDR(VENC_UPSAMPLE_CTRL2)
#define P_TCON_INVERT_CTL 		CBUS_REG_ADDR(TCON_INVERT_CTL)
#define P_VENC_VIDEO_PROG_MODE 		CBUS_REG_ADDR(VENC_VIDEO_PROG_MODE)
#define P_VENC_ENCI_LINE 		CBUS_REG_ADDR(VENC_ENCI_LINE)
#define P_VENC_ENCI_PIXEL 		CBUS_REG_ADDR(VENC_ENCI_PIXEL)
#define P_VENC_ENCP_LINE 		CBUS_REG_ADDR(VENC_ENCP_LINE)
#define P_VENC_ENCP_PIXEL 		CBUS_REG_ADDR(VENC_ENCP_PIXEL)
#define P_VENC_STATA 		CBUS_REG_ADDR(VENC_STATA)
#define P_VENC_INTCTRL 		CBUS_REG_ADDR(VENC_INTCTRL)
#define P_VENC_INTFLAG 		CBUS_REG_ADDR(VENC_INTFLAG)
#define P_VENC_VIDEO_TST_EN 		CBUS_REG_ADDR(VENC_VIDEO_TST_EN)
#define P_VENC_VIDEO_TST_MDSEL 		CBUS_REG_ADDR(VENC_VIDEO_TST_MDSEL)
#define P_VENC_VIDEO_TST_Y 		CBUS_REG_ADDR(VENC_VIDEO_TST_Y)
#define P_VENC_VIDEO_TST_CB 		CBUS_REG_ADDR(VENC_VIDEO_TST_CB)
#define P_VENC_VIDEO_TST_CR 		CBUS_REG_ADDR(VENC_VIDEO_TST_CR)
#define P_VENC_VIDEO_TST_CLRBAR_STRT 		CBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_STRT)
#define P_VENC_VIDEO_TST_CLRBAR_WIDTH 		CBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_WIDTH)
#define P_VENC_VIDEO_TST_VDCNT_STSET 		CBUS_REG_ADDR(VENC_VIDEO_TST_VDCNT_STSET)
#define P_VENC_VDAC_DACSEL0 		CBUS_REG_ADDR(VENC_VDAC_DACSEL0)
#define P_VENC_VDAC_DACSEL1 		CBUS_REG_ADDR(VENC_VDAC_DACSEL1)
#define P_VENC_VDAC_DACSEL2 		CBUS_REG_ADDR(VENC_VDAC_DACSEL2)
#define P_VENC_VDAC_DACSEL3 		CBUS_REG_ADDR(VENC_VDAC_DACSEL3)
#define P_VENC_VDAC_DACSEL4 		CBUS_REG_ADDR(VENC_VDAC_DACSEL4)
#define P_VENC_VDAC_DACSEL5 		CBUS_REG_ADDR(VENC_VDAC_DACSEL5)
#define P_VENC_VDAC_SETTING 		CBUS_REG_ADDR(VENC_VDAC_SETTING)
#define P_VENC_VDAC_TST_VAL 		CBUS_REG_ADDR(VENC_VDAC_TST_VAL)
#define P_VENC_VDAC_DAC0_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC0_GAINCTRL)
#define P_VENC_VDAC_DAC0_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC0_OFFSET)
#define P_VENC_VDAC_DAC1_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC1_GAINCTRL)
#define P_VENC_VDAC_DAC1_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC1_OFFSET)
#define P_VENC_VDAC_DAC2_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC2_GAINCTRL)
#define P_VENC_VDAC_DAC2_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC2_OFFSET)
#define P_VENC_VDAC_DAC3_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC3_GAINCTRL)
#define P_VENC_VDAC_DAC3_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC3_OFFSET)
#define P_VENC_VDAC_DAC4_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC4_GAINCTRL)
#define P_VENC_VDAC_DAC4_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC4_OFFSET)
#define P_VENC_VDAC_DAC5_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC5_GAINCTRL)
#define P_VENC_VDAC_DAC5_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC5_OFFSET)
#define P_VENC_VDAC_FIFO_CTRL 		CBUS_REG_ADDR(VENC_VDAC_FIFO_CTRL)
#define P_ENCL_TCON_INVERT_CTL 		CBUS_REG_ADDR(ENCL_TCON_INVERT_CTL)
#define P_ENCP_VIDEO_EN 		CBUS_REG_ADDR(ENCP_VIDEO_EN)
#define P_ENCP_VIDEO_SYNC_MODE 		CBUS_REG_ADDR(ENCP_VIDEO_SYNC_MODE)
#define P_ENCP_MACV_EN 		CBUS_REG_ADDR(ENCP_MACV_EN)
#define P_ENCP_VIDEO_Y_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_Y_SCL)
#define P_ENCP_VIDEO_PB_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_PB_SCL)
#define P_ENCP_VIDEO_PR_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_PR_SCL)
#define P_ENCP_VIDEO_SYNC_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_SYNC_SCL)
#define P_ENCP_VIDEO_MACV_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_MACV_SCL)
#define P_ENCP_VIDEO_Y_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_Y_OFFST)
#define P_ENCP_VIDEO_PB_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_PB_OFFST)
#define P_ENCP_VIDEO_PR_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_PR_OFFST)
#define P_ENCP_VIDEO_SYNC_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_SYNC_OFFST)
#define P_ENCP_VIDEO_MACV_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_MACV_OFFST)
#define P_ENCP_VIDEO_MODE 		CBUS_REG_ADDR(ENCP_VIDEO_MODE)
#define P_ENCP_VIDEO_MODE_ADV 		CBUS_REG_ADDR(ENCP_VIDEO_MODE_ADV)
#define P_ENCP_DBG_PX_RST 		CBUS_REG_ADDR(ENCP_DBG_PX_RST)
#define P_ENCP_DBG_LN_RST 		CBUS_REG_ADDR(ENCP_DBG_LN_RST)
#define P_ENCP_DBG_PX_INT 		CBUS_REG_ADDR(ENCP_DBG_PX_INT)
#define P_ENCP_DBG_LN_INT 		CBUS_REG_ADDR(ENCP_DBG_LN_INT)
#define P_ENCP_VIDEO_YFP1_HTIME 		CBUS_REG_ADDR(ENCP_VIDEO_YFP1_HTIME)
#define P_ENCP_VIDEO_YFP2_HTIME 		CBUS_REG_ADDR(ENCP_VIDEO_YFP2_HTIME)
#define P_ENCP_VIDEO_YC_DLY 		CBUS_REG_ADDR(ENCP_VIDEO_YC_DLY)
#define P_ENCP_VIDEO_MAX_PXCNT 		CBUS_REG_ADDR(ENCP_VIDEO_MAX_PXCNT)
#define P_ENCP_VIDEO_HSPULS_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_HSPULS_BEGIN)
#define P_ENCP_VIDEO_HSPULS_END 		CBUS_REG_ADDR(ENCP_VIDEO_HSPULS_END)
#define P_ENCP_VIDEO_HSPULS_SWITCH 		CBUS_REG_ADDR(ENCP_VIDEO_HSPULS_SWITCH)
#define P_ENCP_VIDEO_VSPULS_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BEGIN)
#define P_ENCP_VIDEO_VSPULS_END 		CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_END)
#define P_ENCP_VIDEO_VSPULS_BLINE 		CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BLINE)
#define P_ENCP_VIDEO_VSPULS_ELINE 		CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_ELINE)
#define P_ENCP_VIDEO_EQPULS_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BEGIN)
#define P_ENCP_VIDEO_EQPULS_END 		CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_END)
#define P_ENCP_VIDEO_EQPULS_BLINE 		CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BLINE)
#define P_ENCP_VIDEO_EQPULS_ELINE 		CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_ELINE)
#define P_ENCP_VIDEO_HAVON_END 		CBUS_REG_ADDR(ENCP_VIDEO_HAVON_END)
#define P_ENCP_VIDEO_HAVON_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_HAVON_BEGIN)
#define P_ENCP_VIDEO_VAVON_ELINE 		CBUS_REG_ADDR(ENCP_VIDEO_VAVON_ELINE)
#define P_ENCP_VIDEO_VAVON_BLINE 		CBUS_REG_ADDR(ENCP_VIDEO_VAVON_BLINE)
#define P_ENCP_VIDEO_HSO_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_HSO_BEGIN)
#define P_ENCP_VIDEO_HSO_END 		CBUS_REG_ADDR(ENCP_VIDEO_HSO_END)
#define P_ENCP_VIDEO_VSO_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_VSO_BEGIN)
#define P_ENCP_VIDEO_VSO_END 		CBUS_REG_ADDR(ENCP_VIDEO_VSO_END)
#define P_ENCP_VIDEO_VSO_BLINE 		CBUS_REG_ADDR(ENCP_VIDEO_VSO_BLINE)
#define P_ENCP_VIDEO_VSO_ELINE 		CBUS_REG_ADDR(ENCP_VIDEO_VSO_ELINE)
#define P_ENCP_VIDEO_SYNC_WAVE_CURVE 		CBUS_REG_ADDR(ENCP_VIDEO_SYNC_WAVE_CURVE)
#define P_ENCP_VIDEO_MAX_LNCNT 		CBUS_REG_ADDR(ENCP_VIDEO_MAX_LNCNT)
#define P_ENCP_VIDEO_SY_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_SY_VAL)
#define P_ENCP_VIDEO_SY2_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_SY2_VAL)
#define P_ENCP_VIDEO_BLANKY_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_BLANKY_VAL)
#define P_ENCP_VIDEO_BLANKPB_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_BLANKPB_VAL)
#define P_ENCP_VIDEO_BLANKPR_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_BLANKPR_VAL)
#define P_ENCP_VIDEO_HOFFST 		CBUS_REG_ADDR(ENCP_VIDEO_HOFFST)
#define P_ENCP_VIDEO_VOFFST 		CBUS_REG_ADDR(ENCP_VIDEO_VOFFST)
#define P_ENCP_VIDEO_RGB_CTRL 		CBUS_REG_ADDR(ENCP_VIDEO_RGB_CTRL)
#define P_ENCP_VIDEO_FILT_CTRL 		CBUS_REG_ADDR(ENCP_VIDEO_FILT_CTRL)
#define P_ENCP_VIDEO_OFLD_VPEQ_OFST 		CBUS_REG_ADDR(ENCP_VIDEO_OFLD_VPEQ_OFST)
#define P_ENCP_VIDEO_OFLD_VOAV_OFST 		CBUS_REG_ADDR(ENCP_VIDEO_OFLD_VOAV_OFST)
#define P_ENCP_VIDEO_MATRIX_CB 		CBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CB)
#define P_ENCP_VIDEO_MATRIX_CR 		CBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CR)
#define P_ENCP_VIDEO_RGBIN_CTRL 		CBUS_REG_ADDR(ENCP_VIDEO_RGBIN_CTRL)
#define P_ENCP_MACV_BLANKY_VAL 		CBUS_REG_ADDR(ENCP_MACV_BLANKY_VAL)
#define P_ENCP_MACV_MAXY_VAL 		CBUS_REG_ADDR(ENCP_MACV_MAXY_VAL)
#define P_ENCP_MACV_1ST_PSSYNC_STRT 		CBUS_REG_ADDR(ENCP_MACV_1ST_PSSYNC_STRT)
#define P_ENCP_MACV_PSSYNC_STRT 		CBUS_REG_ADDR(ENCP_MACV_PSSYNC_STRT)
#define P_ENCP_MACV_AGC_STRT 		CBUS_REG_ADDR(ENCP_MACV_AGC_STRT)
#define P_ENCP_MACV_AGC_END 		CBUS_REG_ADDR(ENCP_MACV_AGC_END)
#define P_ENCP_MACV_WAVE_END 		CBUS_REG_ADDR(ENCP_MACV_WAVE_END)
#define P_ENCP_MACV_STRTLINE 		CBUS_REG_ADDR(ENCP_MACV_STRTLINE)
#define P_ENCP_MACV_ENDLINE 		CBUS_REG_ADDR(ENCP_MACV_ENDLINE)
#define P_ENCP_MACV_TS_CNT_MAX_L 		CBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_L)
#define P_ENCP_MACV_TS_CNT_MAX_H 		CBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_H)
#define P_ENCP_MACV_TIME_DOWN 		CBUS_REG_ADDR(ENCP_MACV_TIME_DOWN)
#define P_ENCP_MACV_TIME_LO 		CBUS_REG_ADDR(ENCP_MACV_TIME_LO)
#define P_ENCP_MACV_TIME_UP 		CBUS_REG_ADDR(ENCP_MACV_TIME_UP)
#define P_ENCP_MACV_TIME_RST 		CBUS_REG_ADDR(ENCP_MACV_TIME_RST)
#define P_ENCP_VBI_CTRL 		CBUS_REG_ADDR(ENCP_VBI_CTRL)
#define P_ENCP_VBI_SETTING 		CBUS_REG_ADDR(ENCP_VBI_SETTING)
#define P_ENCP_VBI_BEGIN 		CBUS_REG_ADDR(ENCP_VBI_BEGIN)
#define P_ENCP_VBI_WIDTH 		CBUS_REG_ADDR(ENCP_VBI_WIDTH)
#define P_ENCP_VBI_HVAL 		CBUS_REG_ADDR(ENCP_VBI_HVAL)
#define P_ENCP_VBI_DATA0 		CBUS_REG_ADDR(ENCP_VBI_DATA0)
#define P_ENCP_VBI_DATA1 		CBUS_REG_ADDR(ENCP_VBI_DATA1)
#define P_C656_HS_ST 		CBUS_REG_ADDR(C656_HS_ST)
#define P_C656_HS_ED 		CBUS_REG_ADDR(C656_HS_ED)
#define P_C656_VS_LNST_E 		CBUS_REG_ADDR(C656_VS_LNST_E)
#define P_C656_VS_LNST_O 		CBUS_REG_ADDR(C656_VS_LNST_O)
#define P_C656_VS_LNED_E 		CBUS_REG_ADDR(C656_VS_LNED_E)
#define P_C656_VS_LNED_O 		CBUS_REG_ADDR(C656_VS_LNED_O)
#define P_C656_FS_LNST 		CBUS_REG_ADDR(C656_FS_LNST)
#define P_C656_FS_LNED 		CBUS_REG_ADDR(C656_FS_LNED)
#define P_ENCI_VIDEO_MODE 		CBUS_REG_ADDR(ENCI_VIDEO_MODE)
#define P_ENCI_VIDEO_MODE_ADV 		CBUS_REG_ADDR(ENCI_VIDEO_MODE_ADV)
#define P_ENCI_VIDEO_FSC_ADJ 		CBUS_REG_ADDR(ENCI_VIDEO_FSC_ADJ)
#define P_ENCI_VIDEO_BRIGHT 		CBUS_REG_ADDR(ENCI_VIDEO_BRIGHT)
#define P_ENCI_VIDEO_CONT 		CBUS_REG_ADDR(ENCI_VIDEO_CONT)
#define P_ENCI_VIDEO_SAT 		CBUS_REG_ADDR(ENCI_VIDEO_SAT)
#define P_ENCI_VIDEO_HUE 		CBUS_REG_ADDR(ENCI_VIDEO_HUE)
#define P_ENCI_VIDEO_SCH 		CBUS_REG_ADDR(ENCI_VIDEO_SCH)
#define P_ENCI_SYNC_MODE 		CBUS_REG_ADDR(ENCI_SYNC_MODE)
#define P_ENCI_SYNC_CTRL 		CBUS_REG_ADDR(ENCI_SYNC_CTRL)
#define P_ENCI_SYNC_HSO_BEGIN 		CBUS_REG_ADDR(ENCI_SYNC_HSO_BEGIN)
#define P_ENCI_SYNC_HSO_END 		CBUS_REG_ADDR(ENCI_SYNC_HSO_END)
#define P_ENCI_SYNC_VSO_EVN 		CBUS_REG_ADDR(ENCI_SYNC_VSO_EVN)
#define P_ENCI_SYNC_VSO_ODD 		CBUS_REG_ADDR(ENCI_SYNC_VSO_ODD)
#define P_ENCI_SYNC_VSO_EVNLN 		CBUS_REG_ADDR(ENCI_SYNC_VSO_EVNLN)
#define P_ENCI_SYNC_VSO_ODDLN 		CBUS_REG_ADDR(ENCI_SYNC_VSO_ODDLN)
#define P_ENCI_SYNC_HOFFST 		CBUS_REG_ADDR(ENCI_SYNC_HOFFST)
#define P_ENCI_SYNC_VOFFST 		CBUS_REG_ADDR(ENCI_SYNC_VOFFST)
#define P_ENCI_SYNC_ADJ 		CBUS_REG_ADDR(ENCI_SYNC_ADJ)
#define P_ENCI_RGB_SETTING 		CBUS_REG_ADDR(ENCI_RGB_SETTING)
#define P_ENCI_DE_H_BEGIN 		CBUS_REG_ADDR(ENCI_DE_H_BEGIN)
#define P_ENCI_DE_H_END 		CBUS_REG_ADDR(ENCI_DE_H_END)
#define P_ENCI_DE_V_BEGIN_EVEN 		CBUS_REG_ADDR(ENCI_DE_V_BEGIN_EVEN)
#define P_ENCI_DE_V_END_EVEN 		CBUS_REG_ADDR(ENCI_DE_V_END_EVEN)
#define P_ENCI_DE_V_BEGIN_ODD 		CBUS_REG_ADDR(ENCI_DE_V_BEGIN_ODD)
#define P_ENCI_DE_V_END_ODD 		CBUS_REG_ADDR(ENCI_DE_V_END_ODD)
#define P_ENCI_VBI_SETTING 		CBUS_REG_ADDR(ENCI_VBI_SETTING)
#define P_ENCI_VBI_CCDT_EVN 		CBUS_REG_ADDR(ENCI_VBI_CCDT_EVN)
#define P_ENCI_VBI_CCDT_ODD 		CBUS_REG_ADDR(ENCI_VBI_CCDT_ODD)
#define P_ENCI_VBI_CC525_LN 		CBUS_REG_ADDR(ENCI_VBI_CC525_LN)
#define P_ENCI_VBI_CC625_LN 		CBUS_REG_ADDR(ENCI_VBI_CC625_LN)
#define P_ENCI_VBI_WSSDT 		CBUS_REG_ADDR(ENCI_VBI_WSSDT)
#define P_ENCI_VBI_WSS_LN 		CBUS_REG_ADDR(ENCI_VBI_WSS_LN)
#define P_ENCI_VBI_CGMSDT_L 		CBUS_REG_ADDR(ENCI_VBI_CGMSDT_L)
#define P_ENCI_VBI_CGMSDT_H 		CBUS_REG_ADDR(ENCI_VBI_CGMSDT_H)
#define P_ENCI_VBI_CGMS_LN 		CBUS_REG_ADDR(ENCI_VBI_CGMS_LN)
#define P_ENCI_VBI_TTX_HTIME 		CBUS_REG_ADDR(ENCI_VBI_TTX_HTIME)
#define P_ENCI_VBI_TTX_LN 		CBUS_REG_ADDR(ENCI_VBI_TTX_LN)
#define P_ENCI_VBI_TTXDT0 		CBUS_REG_ADDR(ENCI_VBI_TTXDT0)
#define P_ENCI_VBI_TTXDT1 		CBUS_REG_ADDR(ENCI_VBI_TTXDT1)
#define P_ENCI_VBI_TTXDT2 		CBUS_REG_ADDR(ENCI_VBI_TTXDT2)
#define P_ENCI_VBI_TTXDT3 		CBUS_REG_ADDR(ENCI_VBI_TTXDT3)
#define P_ENCI_MACV_N0 		CBUS_REG_ADDR(ENCI_MACV_N0)
#define P_ENCI_MACV_N1 		CBUS_REG_ADDR(ENCI_MACV_N1)
#define P_ENCI_MACV_N2 		CBUS_REG_ADDR(ENCI_MACV_N2)
#define P_ENCI_MACV_N3 		CBUS_REG_ADDR(ENCI_MACV_N3)
#define P_ENCI_MACV_N4 		CBUS_REG_ADDR(ENCI_MACV_N4)
#define P_ENCI_MACV_N5 		CBUS_REG_ADDR(ENCI_MACV_N5)
#define P_ENCI_MACV_N6 		CBUS_REG_ADDR(ENCI_MACV_N6)
#define P_ENCI_MACV_N7 		CBUS_REG_ADDR(ENCI_MACV_N7)
#define P_ENCI_MACV_N8 		CBUS_REG_ADDR(ENCI_MACV_N8)
#define P_ENCI_MACV_N9 		CBUS_REG_ADDR(ENCI_MACV_N9)
#define P_ENCI_MACV_N10 		CBUS_REG_ADDR(ENCI_MACV_N10)
#define P_ENCI_MACV_N11 		CBUS_REG_ADDR(ENCI_MACV_N11)
#define P_ENCI_MACV_N12 		CBUS_REG_ADDR(ENCI_MACV_N12)
#define P_ENCI_MACV_N13 		CBUS_REG_ADDR(ENCI_MACV_N13)
#define P_ENCI_MACV_N14 		CBUS_REG_ADDR(ENCI_MACV_N14)
#define P_ENCI_MACV_N15 		CBUS_REG_ADDR(ENCI_MACV_N15)
#define P_ENCI_MACV_N16 		CBUS_REG_ADDR(ENCI_MACV_N16)
#define P_ENCI_MACV_N17 		CBUS_REG_ADDR(ENCI_MACV_N17)
#define P_ENCI_MACV_N18 		CBUS_REG_ADDR(ENCI_MACV_N18)
#define P_ENCI_MACV_N19 		CBUS_REG_ADDR(ENCI_MACV_N19)
#define P_ENCI_MACV_N20 		CBUS_REG_ADDR(ENCI_MACV_N20)
#define P_ENCI_MACV_N21 		CBUS_REG_ADDR(ENCI_MACV_N21)
#define P_ENCI_MACV_N22 		CBUS_REG_ADDR(ENCI_MACV_N22)
#define P_ENCI_DBG_PX_RST 		CBUS_REG_ADDR(ENCI_DBG_PX_RST)
#define P_ENCI_DBG_FLDLN_RST 		CBUS_REG_ADDR(ENCI_DBG_FLDLN_RST)
#define P_ENCI_DBG_PX_INT 		CBUS_REG_ADDR(ENCI_DBG_PX_INT)
#define P_ENCI_DBG_FLDLN_INT 		CBUS_REG_ADDR(ENCI_DBG_FLDLN_INT)
#define P_ENCI_DBG_MAXPX 		CBUS_REG_ADDR(ENCI_DBG_MAXPX)
#define P_ENCI_DBG_MAXLN 		CBUS_REG_ADDR(ENCI_DBG_MAXLN)
#define P_ENCI_MACV_MAX_AMP 		CBUS_REG_ADDR(ENCI_MACV_MAX_AMP)
#define P_ENCI_MACV_PULSE_LO 		CBUS_REG_ADDR(ENCI_MACV_PULSE_LO)
#define P_ENCI_MACV_PULSE_HI 		CBUS_REG_ADDR(ENCI_MACV_PULSE_HI)
#define P_ENCI_MACV_BKP_MAX 		CBUS_REG_ADDR(ENCI_MACV_BKP_MAX)
#define P_ENCI_CFILT_CTRL 		CBUS_REG_ADDR(ENCI_CFILT_CTRL)
#define P_ENCI_CFILT7 		CBUS_REG_ADDR(ENCI_CFILT7)
#define P_ENCI_YC_DELAY 		CBUS_REG_ADDR(ENCI_YC_DELAY)
#define P_ENCI_VIDEO_EN 		CBUS_REG_ADDR(ENCI_VIDEO_EN)
#define P_ENCI_DVI_HSO_BEGIN 		CBUS_REG_ADDR(ENCI_DVI_HSO_BEGIN)
#define P_ENCI_DVI_HSO_END 		CBUS_REG_ADDR(ENCI_DVI_HSO_END)
#define P_ENCI_DVI_VSO_BLINE_EVN 		CBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_EVN)
#define P_ENCI_DVI_VSO_BLINE_ODD 		CBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_ODD)
#define P_ENCI_DVI_VSO_ELINE_EVN 		CBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_EVN)
#define P_ENCI_DVI_VSO_ELINE_ODD 		CBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_ODD)
#define P_ENCI_DVI_VSO_BEGIN_EVN 		CBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_EVN)
#define P_ENCI_DVI_VSO_BEGIN_ODD 		CBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_ODD)
#define P_ENCI_DVI_VSO_END_EVN 		CBUS_REG_ADDR(ENCI_DVI_VSO_END_EVN)
#define P_ENCI_DVI_VSO_END_ODD 		CBUS_REG_ADDR(ENCI_DVI_VSO_END_ODD)
#define P_ENCI_CFILT_CTRL2 		CBUS_REG_ADDR(ENCI_CFILT_CTRL2)
#define P_ENCI_DACSEL_0 		CBUS_REG_ADDR(ENCI_DACSEL_0)
#define P_ENCI_DACSEL_1 		CBUS_REG_ADDR(ENCI_DACSEL_1)
#define P_ENCP_DACSEL_0 		CBUS_REG_ADDR(ENCP_DACSEL_0)
#define P_ENCP_DACSEL_1 		CBUS_REG_ADDR(ENCP_DACSEL_1)
#define P_ENCP_MAX_LINE_SWITCH_POINT 		CBUS_REG_ADDR(ENCP_MAX_LINE_SWITCH_POINT)
#define P_ENCI_TST_EN 		CBUS_REG_ADDR(ENCI_TST_EN)
#define P_ENCI_TST_MDSEL 		CBUS_REG_ADDR(ENCI_TST_MDSEL)
#define P_ENCI_TST_Y 		CBUS_REG_ADDR(ENCI_TST_Y)
#define P_ENCI_TST_CB 		CBUS_REG_ADDR(ENCI_TST_CB)
#define P_ENCI_TST_CR 		CBUS_REG_ADDR(ENCI_TST_CR)
#define P_ENCI_TST_CLRBAR_STRT 		CBUS_REG_ADDR(ENCI_TST_CLRBAR_STRT)
#define P_ENCI_TST_CLRBAR_WIDTH 		CBUS_REG_ADDR(ENCI_TST_CLRBAR_WIDTH)
#define P_ENCI_TST_VDCNT_STSET 		CBUS_REG_ADDR(ENCI_TST_VDCNT_STSET)
#define P_ENCI_VFIFO2VD_CTL 		CBUS_REG_ADDR(ENCI_VFIFO2VD_CTL)
#define P_ENCI_VFIFO2VD_PIXEL_START 		CBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_START)
#define P_ENCI_VFIFO2VD_PIXEL_END 		CBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_END)
#define P_ENCI_VFIFO2VD_LINE_TOP_START 		CBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_START)
#define P_ENCI_VFIFO2VD_LINE_TOP_END 		CBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_END)
#define P_ENCI_VFIFO2VD_LINE_BOT_START 		CBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_START)
#define P_ENCI_VFIFO2VD_LINE_BOT_END 		CBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_END)
#define P_ENCI_VFIFO2VD_CTL2 		CBUS_REG_ADDR(ENCI_VFIFO2VD_CTL2)
#define P_ENCT_VFIFO2VD_CTL 		CBUS_REG_ADDR(ENCT_VFIFO2VD_CTL)
#define P_ENCT_VFIFO2VD_PIXEL_START 		CBUS_REG_ADDR(ENCT_VFIFO2VD_PIXEL_START)
#define P_ENCT_VFIFO2VD_PIXEL_END 		CBUS_REG_ADDR(ENCT_VFIFO2VD_PIXEL_END)
#define P_ENCT_VFIFO2VD_LINE_TOP_START 		CBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_TOP_START)
#define P_ENCT_VFIFO2VD_LINE_TOP_END 		CBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_TOP_END)
#define P_ENCT_VFIFO2VD_LINE_BOT_START 		CBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_BOT_START)
#define P_ENCT_VFIFO2VD_LINE_BOT_END 		CBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_BOT_END)
#define P_ENCT_VFIFO2VD_CTL2 		CBUS_REG_ADDR(ENCT_VFIFO2VD_CTL2)
#define P_ENCT_TST_EN 		CBUS_REG_ADDR(ENCT_TST_EN)
#define P_ENCT_TST_MDSEL 		CBUS_REG_ADDR(ENCT_TST_MDSEL)
#define P_ENCT_TST_Y 		CBUS_REG_ADDR(ENCT_TST_Y)
#define P_ENCT_TST_CB 		CBUS_REG_ADDR(ENCT_TST_CB)
#define P_ENCT_TST_CR 		CBUS_REG_ADDR(ENCT_TST_CR)
#define P_ENCT_TST_CLRBAR_STRT 		CBUS_REG_ADDR(ENCT_TST_CLRBAR_STRT)
#define P_ENCT_TST_CLRBAR_WIDTH 		CBUS_REG_ADDR(ENCT_TST_CLRBAR_WIDTH)
#define P_ENCT_TST_VDCNT_STSET 		CBUS_REG_ADDR(ENCT_TST_VDCNT_STSET)
#define P_ENCP_DVI_HSO_BEGIN 		CBUS_REG_ADDR(ENCP_DVI_HSO_BEGIN)
#define P_ENCP_DVI_HSO_END 		CBUS_REG_ADDR(ENCP_DVI_HSO_END)
#define P_ENCP_DVI_VSO_BLINE_EVN 		CBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_EVN)
#define P_ENCP_DVI_VSO_BLINE_ODD 		CBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_ODD)
#define P_ENCP_DVI_VSO_ELINE_EVN 		CBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_EVN)
#define P_ENCP_DVI_VSO_ELINE_ODD 		CBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_ODD)
#define P_ENCP_DVI_VSO_BEGIN_EVN 		CBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_EVN)
#define P_ENCP_DVI_VSO_BEGIN_ODD 		CBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_ODD)
#define P_ENCP_DVI_VSO_END_EVN 		CBUS_REG_ADDR(ENCP_DVI_VSO_END_EVN)
#define P_ENCP_DVI_VSO_END_ODD 		CBUS_REG_ADDR(ENCP_DVI_VSO_END_ODD)
#define P_ENCP_DE_H_BEGIN 		CBUS_REG_ADDR(ENCP_DE_H_BEGIN)
#define P_ENCP_DE_H_END 		CBUS_REG_ADDR(ENCP_DE_H_END)
#define P_ENCP_DE_V_BEGIN_EVEN 		CBUS_REG_ADDR(ENCP_DE_V_BEGIN_EVEN)
#define P_ENCP_DE_V_END_EVEN 		CBUS_REG_ADDR(ENCP_DE_V_END_EVEN)
#define P_ENCP_DE_V_BEGIN_ODD 		CBUS_REG_ADDR(ENCP_DE_V_BEGIN_ODD)
#define P_ENCP_DE_V_END_ODD 		CBUS_REG_ADDR(ENCP_DE_V_END_ODD)
#define P_ENCI_SYNC_LINE_LENGTH 		CBUS_REG_ADDR(ENCI_SYNC_LINE_LENGTH)
#define P_ENCI_SYNC_PIXEL_EN 		CBUS_REG_ADDR(ENCI_SYNC_PIXEL_EN)
#define P_ENCI_SYNC_TO_LINE_EN 		CBUS_REG_ADDR(ENCI_SYNC_TO_LINE_EN)
#define P_ENCI_SYNC_TO_PIXEL 		CBUS_REG_ADDR(ENCI_SYNC_TO_PIXEL)
#define P_ENCP_SYNC_LINE_LENGTH 		CBUS_REG_ADDR(ENCP_SYNC_LINE_LENGTH)
#define P_ENCP_SYNC_PIXEL_EN 		CBUS_REG_ADDR(ENCP_SYNC_PIXEL_EN)
#define P_ENCP_SYNC_TO_LINE_EN 		CBUS_REG_ADDR(ENCP_SYNC_TO_LINE_EN)
#define P_ENCP_SYNC_TO_PIXEL 		CBUS_REG_ADDR(ENCP_SYNC_TO_PIXEL)
#define P_ENCT_SYNC_LINE_LENGTH 		CBUS_REG_ADDR(ENCT_SYNC_LINE_LENGTH)
#define P_ENCT_SYNC_PIXEL_EN 		CBUS_REG_ADDR(ENCT_SYNC_PIXEL_EN)
#define P_ENCT_SYNC_TO_LINE_EN 		CBUS_REG_ADDR(ENCT_SYNC_TO_LINE_EN)
#define P_ENCT_SYNC_TO_PIXEL 		CBUS_REG_ADDR(ENCT_SYNC_TO_PIXEL)
#define P_ENCL_SYNC_LINE_LENGTH 		CBUS_REG_ADDR(ENCL_SYNC_LINE_LENGTH)
#define P_ENCL_SYNC_PIXEL_EN 		CBUS_REG_ADDR(ENCL_SYNC_PIXEL_EN)
#define P_ENCL_SYNC_TO_LINE_EN 		CBUS_REG_ADDR(ENCL_SYNC_TO_LINE_EN)
#define P_ENCL_SYNC_TO_PIXEL 		CBUS_REG_ADDR(ENCL_SYNC_TO_PIXEL)
#define P_ENCP_VFIFO2VD_CTL2 		CBUS_REG_ADDR(ENCP_VFIFO2VD_CTL2)
#define P_VENC_DVI_SETTING_MORE 		CBUS_REG_ADDR(VENC_DVI_SETTING_MORE)
#define P_VENC_VDAC_DAC4_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC4_FILT_CTRL0)
#define P_VENC_VDAC_DAC4_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC4_FILT_CTRL1)
#define P_VENC_VDAC_DAC5_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC5_FILT_CTRL0)
#define P_VENC_VDAC_DAC5_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC5_FILT_CTRL1)
#define P_VENC_VDAC_DAC0_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL0)
#define P_VENC_VDAC_DAC0_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL1)
#define P_VENC_VDAC_DAC1_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL0)
#define P_VENC_VDAC_DAC1_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL1)
#define P_VENC_VDAC_DAC2_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL0)
#define P_VENC_VDAC_DAC2_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL1)
#define P_VENC_VDAC_DAC3_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL0)
#define P_VENC_VDAC_DAC3_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL1)
#define P_ENCT_VIDEO_EN 		CBUS_REG_ADDR(ENCT_VIDEO_EN)
#define P_ENCT_VIDEO_Y_SCL 		CBUS_REG_ADDR(ENCT_VIDEO_Y_SCL)
#define P_ENCT_VIDEO_PB_SCL 		CBUS_REG_ADDR(ENCT_VIDEO_PB_SCL)
#define P_ENCT_VIDEO_PR_SCL 		CBUS_REG_ADDR(ENCT_VIDEO_PR_SCL)
#define P_ENCT_VIDEO_Y_OFFST 		CBUS_REG_ADDR(ENCT_VIDEO_Y_OFFST)
#define P_ENCT_VIDEO_PB_OFFST 		CBUS_REG_ADDR(ENCT_VIDEO_PB_OFFST)
#define P_ENCT_VIDEO_PR_OFFST 		CBUS_REG_ADDR(ENCT_VIDEO_PR_OFFST)
#define P_ENCT_VIDEO_MODE 		CBUS_REG_ADDR(ENCT_VIDEO_MODE)
#define P_ENCT_VIDEO_MODE_ADV 		CBUS_REG_ADDR(ENCT_VIDEO_MODE_ADV)
#define P_ENCT_DBG_PX_RST 		CBUS_REG_ADDR(ENCT_DBG_PX_RST)
#define P_ENCT_DBG_LN_RST 		CBUS_REG_ADDR(ENCT_DBG_LN_RST)
#define P_ENCT_DBG_PX_INT 		CBUS_REG_ADDR(ENCT_DBG_PX_INT)
#define P_ENCT_DBG_LN_INT 		CBUS_REG_ADDR(ENCT_DBG_LN_INT)
#define P_ENCT_VIDEO_YFP1_HTIME 		CBUS_REG_ADDR(ENCT_VIDEO_YFP1_HTIME)
#define P_ENCT_VIDEO_YFP2_HTIME 		CBUS_REG_ADDR(ENCT_VIDEO_YFP2_HTIME)
#define P_ENCT_VIDEO_YC_DLY 		CBUS_REG_ADDR(ENCT_VIDEO_YC_DLY)
#define P_ENCT_VIDEO_MAX_PXCNT 		CBUS_REG_ADDR(ENCT_VIDEO_MAX_PXCNT)
#define P_ENCT_VIDEO_HAVON_END 		CBUS_REG_ADDR(ENCT_VIDEO_HAVON_END)
#define P_ENCT_VIDEO_HAVON_BEGIN 		CBUS_REG_ADDR(ENCT_VIDEO_HAVON_BEGIN)
#define P_ENCT_VIDEO_VAVON_ELINE 		CBUS_REG_ADDR(ENCT_VIDEO_VAVON_ELINE)
#define P_ENCT_VIDEO_VAVON_BLINE 		CBUS_REG_ADDR(ENCT_VIDEO_VAVON_BLINE)
#define P_ENCT_VIDEO_HSO_BEGIN 		CBUS_REG_ADDR(ENCT_VIDEO_HSO_BEGIN)
#define P_ENCT_VIDEO_HSO_END 		CBUS_REG_ADDR(ENCT_VIDEO_HSO_END)
#define P_ENCT_VIDEO_VSO_BEGIN 		CBUS_REG_ADDR(ENCT_VIDEO_VSO_BEGIN)
#define P_ENCT_VIDEO_VSO_END 		CBUS_REG_ADDR(ENCT_VIDEO_VSO_END)
#define P_ENCT_VIDEO_VSO_BLINE 		CBUS_REG_ADDR(ENCT_VIDEO_VSO_BLINE)
#define P_ENCT_VIDEO_VSO_ELINE 		CBUS_REG_ADDR(ENCT_VIDEO_VSO_ELINE)
#define P_ENCT_VIDEO_MAX_LNCNT 		CBUS_REG_ADDR(ENCT_VIDEO_MAX_LNCNT)
#define P_ENCT_VIDEO_BLANKY_VAL 		CBUS_REG_ADDR(ENCT_VIDEO_BLANKY_VAL)
#define P_ENCT_VIDEO_BLANKPB_VAL 		CBUS_REG_ADDR(ENCT_VIDEO_BLANKPB_VAL)
#define P_ENCT_VIDEO_BLANKPR_VAL 		CBUS_REG_ADDR(ENCT_VIDEO_BLANKPR_VAL)
#define P_ENCT_VIDEO_HOFFST 		CBUS_REG_ADDR(ENCT_VIDEO_HOFFST)
#define P_ENCT_VIDEO_VOFFST 		CBUS_REG_ADDR(ENCT_VIDEO_VOFFST)
#define P_ENCT_VIDEO_RGB_CTRL 		CBUS_REG_ADDR(ENCT_VIDEO_RGB_CTRL)
#define P_ENCT_VIDEO_FILT_CTRL 		CBUS_REG_ADDR(ENCT_VIDEO_FILT_CTRL)
#define P_ENCT_VIDEO_OFLD_VPEQ_OFST 		CBUS_REG_ADDR(ENCT_VIDEO_OFLD_VPEQ_OFST)
#define P_ENCT_VIDEO_OFLD_VOAV_OFST 		CBUS_REG_ADDR(ENCT_VIDEO_OFLD_VOAV_OFST)
#define P_ENCT_VIDEO_MATRIX_CB 		CBUS_REG_ADDR(ENCT_VIDEO_MATRIX_CB)
#define P_ENCT_VIDEO_MATRIX_CR 		CBUS_REG_ADDR(ENCT_VIDEO_MATRIX_CR)
#define P_ENCT_VIDEO_RGBIN_CTRL 		CBUS_REG_ADDR(ENCT_VIDEO_RGBIN_CTRL)
#define P_ENCT_MAX_LINE_SWITCH_POINT 		CBUS_REG_ADDR(ENCT_MAX_LINE_SWITCH_POINT)
#define P_ENCT_DACSEL_0 		CBUS_REG_ADDR(ENCT_DACSEL_0)
#define P_ENCT_DACSEL_1 		CBUS_REG_ADDR(ENCT_DACSEL_1)
#define P_ENCL_VFIFO2VD_CTL 		CBUS_REG_ADDR(ENCL_VFIFO2VD_CTL)
#define P_ENCL_VFIFO2VD_PIXEL_START 		CBUS_REG_ADDR(ENCL_VFIFO2VD_PIXEL_START)
#define P_ENCL_VFIFO2VD_PIXEL_END 		CBUS_REG_ADDR(ENCL_VFIFO2VD_PIXEL_END)
#define P_ENCL_VFIFO2VD_LINE_TOP_START 		CBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_TOP_START)
#define P_ENCL_VFIFO2VD_LINE_TOP_END 		CBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_TOP_END)
#define P_ENCL_VFIFO2VD_LINE_BOT_START 		CBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_BOT_START)
#define P_ENCL_VFIFO2VD_LINE_BOT_END 		CBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_BOT_END)
#define P_ENCL_VFIFO2VD_CTL2 		CBUS_REG_ADDR(ENCL_VFIFO2VD_CTL2)
#define P_ENCL_TST_EN 		CBUS_REG_ADDR(ENCL_TST_EN)
#define P_ENCL_TST_MDSEL 		CBUS_REG_ADDR(ENCL_TST_MDSEL)
#define P_ENCL_TST_Y 		CBUS_REG_ADDR(ENCL_TST_Y)
#define P_ENCL_TST_CB 		CBUS_REG_ADDR(ENCL_TST_CB)
#define P_ENCL_TST_CR 		CBUS_REG_ADDR(ENCL_TST_CR)
#define P_ENCL_TST_CLRBAR_STRT 		CBUS_REG_ADDR(ENCL_TST_CLRBAR_STRT)
#define P_ENCL_TST_CLRBAR_WIDTH 		CBUS_REG_ADDR(ENCL_TST_CLRBAR_WIDTH)
#define P_ENCL_TST_VDCNT_STSET 		CBUS_REG_ADDR(ENCL_TST_VDCNT_STSET)
#define P_ENCL_VIDEO_EN 		CBUS_REG_ADDR(ENCL_VIDEO_EN)
#define P_ENCL_VIDEO_Y_SCL 		CBUS_REG_ADDR(ENCL_VIDEO_Y_SCL)
#define P_ENCL_VIDEO_PB_SCL 		CBUS_REG_ADDR(ENCL_VIDEO_PB_SCL)
#define P_ENCL_VIDEO_PR_SCL 		CBUS_REG_ADDR(ENCL_VIDEO_PR_SCL)
#define P_ENCL_VIDEO_Y_OFFST 		CBUS_REG_ADDR(ENCL_VIDEO_Y_OFFST)
#define P_ENCL_VIDEO_PB_OFFST 		CBUS_REG_ADDR(ENCL_VIDEO_PB_OFFST)
#define P_ENCL_VIDEO_PR_OFFST 		CBUS_REG_ADDR(ENCL_VIDEO_PR_OFFST)
#define P_ENCL_VIDEO_MODE 		CBUS_REG_ADDR(ENCL_VIDEO_MODE)
#define P_ENCL_VIDEO_MODE_ADV 		CBUS_REG_ADDR(ENCL_VIDEO_MODE_ADV)
#define P_ENCL_DBG_PX_RST 		CBUS_REG_ADDR(ENCL_DBG_PX_RST)
#define P_ENCL_DBG_LN_RST 		CBUS_REG_ADDR(ENCL_DBG_LN_RST)
#define P_ENCL_DBG_PX_INT 		CBUS_REG_ADDR(ENCL_DBG_PX_INT)
#define P_ENCL_DBG_LN_INT 		CBUS_REG_ADDR(ENCL_DBG_LN_INT)
#define P_ENCL_VIDEO_YFP1_HTIME 		CBUS_REG_ADDR(ENCL_VIDEO_YFP1_HTIME)
#define P_ENCL_VIDEO_YFP2_HTIME 		CBUS_REG_ADDR(ENCL_VIDEO_YFP2_HTIME)
#define P_ENCL_VIDEO_YC_DLY 		CBUS_REG_ADDR(ENCL_VIDEO_YC_DLY)
#define P_ENCL_VIDEO_MAX_PXCNT 		CBUS_REG_ADDR(ENCL_VIDEO_MAX_PXCNT)
#define P_ENCL_VIDEO_HAVON_END 		CBUS_REG_ADDR(ENCL_VIDEO_HAVON_END)
#define P_ENCL_VIDEO_HAVON_BEGIN 		CBUS_REG_ADDR(ENCL_VIDEO_HAVON_BEGIN)
#define P_ENCL_VIDEO_VAVON_ELINE 		CBUS_REG_ADDR(ENCL_VIDEO_VAVON_ELINE)
#define P_ENCL_VIDEO_VAVON_BLINE 		CBUS_REG_ADDR(ENCL_VIDEO_VAVON_BLINE)
#define P_ENCL_VIDEO_HSO_BEGIN 		CBUS_REG_ADDR(ENCL_VIDEO_HSO_BEGIN)
#define P_ENCL_VIDEO_HSO_END 		CBUS_REG_ADDR(ENCL_VIDEO_HSO_END)
#define P_ENCL_VIDEO_VSO_BEGIN 		CBUS_REG_ADDR(ENCL_VIDEO_VSO_BEGIN)
#define P_ENCL_VIDEO_VSO_END 		CBUS_REG_ADDR(ENCL_VIDEO_VSO_END)
#define P_ENCL_VIDEO_VSO_BLINE 		CBUS_REG_ADDR(ENCL_VIDEO_VSO_BLINE)
#define P_ENCL_VIDEO_VSO_ELINE 		CBUS_REG_ADDR(ENCL_VIDEO_VSO_ELINE)
#define P_ENCL_VIDEO_MAX_LNCNT 		CBUS_REG_ADDR(ENCL_VIDEO_MAX_LNCNT)
#define P_ENCL_VIDEO_BLANKY_VAL 		CBUS_REG_ADDR(ENCL_VIDEO_BLANKY_VAL)
#define P_ENCL_VIDEO_BLANKPB_VAL 		CBUS_REG_ADDR(ENCL_VIDEO_BLANKPB_VAL)
#define P_ENCL_VIDEO_BLANKPR_VAL 		CBUS_REG_ADDR(ENCL_VIDEO_BLANKPR_VAL)
#define P_ENCL_VIDEO_HOFFST 		CBUS_REG_ADDR(ENCL_VIDEO_HOFFST)
#define P_ENCL_VIDEO_VOFFST 		CBUS_REG_ADDR(ENCL_VIDEO_VOFFST)
#define P_ENCL_VIDEO_RGB_CTRL 		CBUS_REG_ADDR(ENCL_VIDEO_RGB_CTRL)
#define P_ENCL_VIDEO_FILT_CTRL 		CBUS_REG_ADDR(ENCL_VIDEO_FILT_CTRL)
#define P_ENCL_VIDEO_OFLD_VPEQ_OFST 		CBUS_REG_ADDR(ENCL_VIDEO_OFLD_VPEQ_OFST)
#define P_ENCL_VIDEO_OFLD_VOAV_OFST 		CBUS_REG_ADDR(ENCL_VIDEO_OFLD_VOAV_OFST)
#define P_ENCL_VIDEO_MATRIX_CB 		CBUS_REG_ADDR(ENCL_VIDEO_MATRIX_CB)
#define P_ENCL_VIDEO_MATRIX_CR 		CBUS_REG_ADDR(ENCL_VIDEO_MATRIX_CR)
#define P_ENCL_VIDEO_RGBIN_CTRL 		CBUS_REG_ADDR(ENCL_VIDEO_RGBIN_CTRL)
#define P_ENCL_MAX_LINE_SWITCH_POINT 		CBUS_REG_ADDR(ENCL_MAX_LINE_SWITCH_POINT)
#define P_ENCL_DACSEL_0 		CBUS_REG_ADDR(ENCL_DACSEL_0)
#define P_ENCL_DACSEL_1 		CBUS_REG_ADDR(ENCL_DACSEL_1)
#define P_RDMA_AHB_START_ADDR_MAN 		CBUS_REG_ADDR(RDMA_AHB_START_ADDR_MAN)
#define P_RDMA_AHB_END_ADDR_MAN 		CBUS_REG_ADDR(RDMA_AHB_END_ADDR_MAN)
#define P_RDMA_AHB_START_ADDR_1 		CBUS_REG_ADDR(RDMA_AHB_START_ADDR_1)
#define P_RDMA_AHB_END_ADDR_1 		CBUS_REG_ADDR(RDMA_AHB_END_ADDR_1)
#define P_RDMA_AHB_START_ADDR_2 		CBUS_REG_ADDR(RDMA_AHB_START_ADDR_2)
#define P_RDMA_AHB_END_ADDR_2 		CBUS_REG_ADDR(RDMA_AHB_END_ADDR_2)
#define P_RDMA_AHB_START_ADDR_3 		CBUS_REG_ADDR(RDMA_AHB_START_ADDR_3)
#define P_RDMA_AHB_END_ADDR_3 		CBUS_REG_ADDR(RDMA_AHB_END_ADDR_3)
#define P_RDMA_ACCESS_AUTO 		CBUS_REG_ADDR(RDMA_ACCESS_AUTO)
#define P_RDMA_ACCESS_MAN 		CBUS_REG_ADDR(RDMA_ACCESS_MAN)
#define P_RDMA_CTRL 		CBUS_REG_ADDR(RDMA_CTRL)
#define P_RDMA_STATUS 		CBUS_REG_ADDR(RDMA_STATUS)
#define P_L_GAMMA_CNTL_PORT 		CBUS_REG_ADDR(L_GAMMA_CNTL_PORT)
#define P_L_GAMMA_DATA_PORT 		CBUS_REG_ADDR(L_GAMMA_DATA_PORT)
#define P_L_GAMMA_ADDR_PORT 		CBUS_REG_ADDR(L_GAMMA_ADDR_PORT)
#define P_L_GAMMA_VCOM_HSWITCH_ADDR 		CBUS_REG_ADDR(L_GAMMA_VCOM_HSWITCH_ADDR)
#define P_L_RGB_BASE_ADDR 		CBUS_REG_ADDR(L_RGB_BASE_ADDR)
#define P_L_RGB_COEFF_ADDR 		CBUS_REG_ADDR(L_RGB_COEFF_ADDR)
#define P_L_POL_CNTL_ADDR 		CBUS_REG_ADDR(L_POL_CNTL_ADDR)
#define P_L_DITH_CNTL_ADDR 		CBUS_REG_ADDR(L_DITH_CNTL_ADDR)
#define P_L_STH1_HS_ADDR 		CBUS_REG_ADDR(L_STH1_HS_ADDR)
#define P_L_STH1_HE_ADDR 		CBUS_REG_ADDR(L_STH1_HE_ADDR)
#define P_L_STH1_VS_ADDR 		CBUS_REG_ADDR(L_STH1_VS_ADDR)
#define P_L_STH1_VE_ADDR 		CBUS_REG_ADDR(L_STH1_VE_ADDR)
#define P_L_STH2_HS_ADDR 		CBUS_REG_ADDR(L_STH2_HS_ADDR)
#define P_L_STH2_HE_ADDR 		CBUS_REG_ADDR(L_STH2_HE_ADDR)
#define P_L_STH2_VS_ADDR 		CBUS_REG_ADDR(L_STH2_VS_ADDR)
#define P_L_STH2_VE_ADDR 		CBUS_REG_ADDR(L_STH2_VE_ADDR)
#define P_L_OEH_HS_ADDR 		CBUS_REG_ADDR(L_OEH_HS_ADDR)
#define P_L_OEH_HE_ADDR 		CBUS_REG_ADDR(L_OEH_HE_ADDR)
#define P_L_OEH_VS_ADDR 		CBUS_REG_ADDR(L_OEH_VS_ADDR)
#define P_L_OEH_VE_ADDR 		CBUS_REG_ADDR(L_OEH_VE_ADDR)
#define P_L_VCOM_HSWITCH_ADDR 		CBUS_REG_ADDR(L_VCOM_HSWITCH_ADDR)
#define P_L_VCOM_VS_ADDR 		CBUS_REG_ADDR(L_VCOM_VS_ADDR)
#define P_L_VCOM_VE_ADDR 		CBUS_REG_ADDR(L_VCOM_VE_ADDR)
#define P_L_CPV1_HS_ADDR 		CBUS_REG_ADDR(L_CPV1_HS_ADDR)
#define P_L_CPV1_HE_ADDR 		CBUS_REG_ADDR(L_CPV1_HE_ADDR)
#define P_L_CPV1_VS_ADDR 		CBUS_REG_ADDR(L_CPV1_VS_ADDR)
#define P_L_CPV1_VE_ADDR 		CBUS_REG_ADDR(L_CPV1_VE_ADDR)
#define P_L_CPV2_HS_ADDR 		CBUS_REG_ADDR(L_CPV2_HS_ADDR)
#define P_L_CPV2_HE_ADDR 		CBUS_REG_ADDR(L_CPV2_HE_ADDR)
#define P_L_CPV2_VS_ADDR 		CBUS_REG_ADDR(L_CPV2_VS_ADDR)
#define P_L_CPV2_VE_ADDR 		CBUS_REG_ADDR(L_CPV2_VE_ADDR)
#define P_L_STV1_HS_ADDR 		CBUS_REG_ADDR(L_STV1_HS_ADDR)
#define P_L_STV1_HE_ADDR 		CBUS_REG_ADDR(L_STV1_HE_ADDR)
#define P_L_STV1_VS_ADDR 		CBUS_REG_ADDR(L_STV1_VS_ADDR)
#define P_L_STV1_VE_ADDR 		CBUS_REG_ADDR(L_STV1_VE_ADDR)
#define P_L_STV2_HS_ADDR 		CBUS_REG_ADDR(L_STV2_HS_ADDR)
#define P_L_STV2_HE_ADDR 		CBUS_REG_ADDR(L_STV2_HE_ADDR)
#define P_L_STV2_VS_ADDR 		CBUS_REG_ADDR(L_STV2_VS_ADDR)
#define P_L_STV2_VE_ADDR 		CBUS_REG_ADDR(L_STV2_VE_ADDR)
#define P_L_OEV1_HS_ADDR 		CBUS_REG_ADDR(L_OEV1_HS_ADDR)
#define P_L_OEV1_HE_ADDR 		CBUS_REG_ADDR(L_OEV1_HE_ADDR)
#define P_L_OEV1_VS_ADDR 		CBUS_REG_ADDR(L_OEV1_VS_ADDR)
#define P_L_OEV1_VE_ADDR 		CBUS_REG_ADDR(L_OEV1_VE_ADDR)
#define P_L_OEV2_HS_ADDR 		CBUS_REG_ADDR(L_OEV2_HS_ADDR)
#define P_L_OEV2_HE_ADDR 		CBUS_REG_ADDR(L_OEV2_HE_ADDR)
#define P_L_OEV2_VS_ADDR 		CBUS_REG_ADDR(L_OEV2_VS_ADDR)
#define P_L_OEV2_VE_ADDR 		CBUS_REG_ADDR(L_OEV2_VE_ADDR)
#define P_L_OEV3_HS_ADDR 		CBUS_REG_ADDR(L_OEV3_HS_ADDR)
#define P_L_OEV3_HE_ADDR 		CBUS_REG_ADDR(L_OEV3_HE_ADDR)
#define P_L_OEV3_VS_ADDR 		CBUS_REG_ADDR(L_OEV3_VS_ADDR)
#define P_L_OEV3_VE_ADDR 		CBUS_REG_ADDR(L_OEV3_VE_ADDR)
#define P_L_LCD_PWR_ADDR 		CBUS_REG_ADDR(L_LCD_PWR_ADDR)
#define P_L_LCD_PWM0_LO_ADDR 		CBUS_REG_ADDR(L_LCD_PWM0_LO_ADDR)
#define P_L_LCD_PWM0_HI_ADDR 		CBUS_REG_ADDR(L_LCD_PWM0_HI_ADDR)
#define P_L_LCD_PWM1_LO_ADDR 		CBUS_REG_ADDR(L_LCD_PWM1_LO_ADDR)
#define P_L_LCD_PWM1_HI_ADDR 		CBUS_REG_ADDR(L_LCD_PWM1_HI_ADDR)
#define P_L_INV_CNT_ADDR 		CBUS_REG_ADDR(L_INV_CNT_ADDR)
#define P_L_TCON_MISC_SEL_ADDR 		CBUS_REG_ADDR(L_TCON_MISC_SEL_ADDR)
#define P_L_DUAL_PORT_CNTL_ADDR 		CBUS_REG_ADDR(L_DUAL_PORT_CNTL_ADDR)
#define P_L_TCON_DOUBLE_CTL 		CBUS_REG_ADDR(L_TCON_DOUBLE_CTL)
#define P_L_TCON_PATTERN_HI 		CBUS_REG_ADDR(L_TCON_PATTERN_HI)
#define P_L_TCON_PATTERN_LO 		CBUS_REG_ADDR(L_TCON_PATTERN_LO)
#define P_L_DE_HS_ADDR 		CBUS_REG_ADDR(L_DE_HS_ADDR)
#define P_L_DE_HE_ADDR 		CBUS_REG_ADDR(L_DE_HE_ADDR)
#define P_L_DE_VS_ADDR 		CBUS_REG_ADDR(L_DE_VS_ADDR)
#define P_L_DE_VE_ADDR 		CBUS_REG_ADDR(L_DE_VE_ADDR)
#define P_L_HSYNC_HS_ADDR 		CBUS_REG_ADDR(L_HSYNC_HS_ADDR)
#define P_L_HSYNC_HE_ADDR 		CBUS_REG_ADDR(L_HSYNC_HE_ADDR)
#define P_L_HSYNC_VS_ADDR 		CBUS_REG_ADDR(L_HSYNC_VS_ADDR)
#define P_L_HSYNC_VE_ADDR 		CBUS_REG_ADDR(L_HSYNC_VE_ADDR)
#define P_L_VSYNC_HS_ADDR 		CBUS_REG_ADDR(L_VSYNC_HS_ADDR)
#define P_L_VSYNC_HE_ADDR 		CBUS_REG_ADDR(L_VSYNC_HE_ADDR)
#define P_L_VSYNC_VS_ADDR 		CBUS_REG_ADDR(L_VSYNC_VS_ADDR)
#define P_L_VSYNC_VE_ADDR 		CBUS_REG_ADDR(L_VSYNC_VE_ADDR)
#define P_L_LCD_MCU_CTL 		CBUS_REG_ADDR(L_LCD_MCU_CTL)
#define P_GAMMA_CNTL_PORT 		CBUS_REG_ADDR(GAMMA_CNTL_PORT)
#define P_GAMMA_DATA_PORT 		CBUS_REG_ADDR(GAMMA_DATA_PORT)
#define P_GAMMA_ADDR_PORT 		CBUS_REG_ADDR(GAMMA_ADDR_PORT)
#define P_GAMMA_VCOM_HSWITCH_ADDR 		CBUS_REG_ADDR(GAMMA_VCOM_HSWITCH_ADDR)
#define P_RGB_BASE_ADDR 		CBUS_REG_ADDR(RGB_BASE_ADDR)
#define P_RGB_COEFF_ADDR 		CBUS_REG_ADDR(RGB_COEFF_ADDR)
#define P_POL_CNTL_ADDR 		CBUS_REG_ADDR(POL_CNTL_ADDR)
#define P_DITH_CNTL_ADDR 		CBUS_REG_ADDR(DITH_CNTL_ADDR)
#define P_STH1_HS_ADDR 		CBUS_REG_ADDR(STH1_HS_ADDR)
#define P_STH1_HE_ADDR 		CBUS_REG_ADDR(STH1_HE_ADDR)
#define P_STH1_VS_ADDR 		CBUS_REG_ADDR(STH1_VS_ADDR)
#define P_STH1_VE_ADDR 		CBUS_REG_ADDR(STH1_VE_ADDR)
#define P_STH2_HS_ADDR 		CBUS_REG_ADDR(STH2_HS_ADDR)
#define P_STH2_HE_ADDR 		CBUS_REG_ADDR(STH2_HE_ADDR)
#define P_STH2_VS_ADDR 		CBUS_REG_ADDR(STH2_VS_ADDR)
#define P_STH2_VE_ADDR 		CBUS_REG_ADDR(STH2_VE_ADDR)
#define P_OEH_HS_ADDR 		CBUS_REG_ADDR(OEH_HS_ADDR)
#define P_OEH_HE_ADDR 		CBUS_REG_ADDR(OEH_HE_ADDR)
#define P_OEH_VS_ADDR 		CBUS_REG_ADDR(OEH_VS_ADDR)
#define P_OEH_VE_ADDR 		CBUS_REG_ADDR(OEH_VE_ADDR)
#define P_VCOM_HSWITCH_ADDR 		CBUS_REG_ADDR(VCOM_HSWITCH_ADDR)
#define P_VCOM_VS_ADDR 		CBUS_REG_ADDR(VCOM_VS_ADDR)
#define P_VCOM_VE_ADDR 		CBUS_REG_ADDR(VCOM_VE_ADDR)
#define P_CPV1_HS_ADDR 		CBUS_REG_ADDR(CPV1_HS_ADDR)
#define P_CPV1_HE_ADDR 		CBUS_REG_ADDR(CPV1_HE_ADDR)
#define P_CPV1_VS_ADDR 		CBUS_REG_ADDR(CPV1_VS_ADDR)
#define P_CPV1_VE_ADDR 		CBUS_REG_ADDR(CPV1_VE_ADDR)
#define P_CPV2_HS_ADDR 		CBUS_REG_ADDR(CPV2_HS_ADDR)
#define P_CPV2_HE_ADDR 		CBUS_REG_ADDR(CPV2_HE_ADDR)
#define P_CPV2_VS_ADDR 		CBUS_REG_ADDR(CPV2_VS_ADDR)
#define P_CPV2_VE_ADDR 		CBUS_REG_ADDR(CPV2_VE_ADDR)
#define P_STV1_HS_ADDR 		CBUS_REG_ADDR(STV1_HS_ADDR)
#define P_STV1_HE_ADDR 		CBUS_REG_ADDR(STV1_HE_ADDR)
#define P_STV1_VS_ADDR 		CBUS_REG_ADDR(STV1_VS_ADDR)
#define P_STV1_VE_ADDR 		CBUS_REG_ADDR(STV1_VE_ADDR)
#define P_STV2_HS_ADDR 		CBUS_REG_ADDR(STV2_HS_ADDR)
#define P_STV2_HE_ADDR 		CBUS_REG_ADDR(STV2_HE_ADDR)
#define P_STV2_VS_ADDR 		CBUS_REG_ADDR(STV2_VS_ADDR)
#define P_STV2_VE_ADDR 		CBUS_REG_ADDR(STV2_VE_ADDR)
#define P_OEV1_HS_ADDR 		CBUS_REG_ADDR(OEV1_HS_ADDR)
#define P_OEV1_HE_ADDR 		CBUS_REG_ADDR(OEV1_HE_ADDR)
#define P_OEV1_VS_ADDR 		CBUS_REG_ADDR(OEV1_VS_ADDR)
#define P_OEV1_VE_ADDR 		CBUS_REG_ADDR(OEV1_VE_ADDR)
#define P_OEV2_HS_ADDR 		CBUS_REG_ADDR(OEV2_HS_ADDR)
#define P_OEV2_HE_ADDR 		CBUS_REG_ADDR(OEV2_HE_ADDR)
#define P_OEV2_VS_ADDR 		CBUS_REG_ADDR(OEV2_VS_ADDR)
#define P_OEV2_VE_ADDR 		CBUS_REG_ADDR(OEV2_VE_ADDR)
#define P_OEV3_HS_ADDR 		CBUS_REG_ADDR(OEV3_HS_ADDR)
#define P_OEV3_HE_ADDR 		CBUS_REG_ADDR(OEV3_HE_ADDR)
#define P_OEV3_VS_ADDR 		CBUS_REG_ADDR(OEV3_VS_ADDR)
#define P_OEV3_VE_ADDR 		CBUS_REG_ADDR(OEV3_VE_ADDR)
#define P_LCD_PWR_ADDR 		CBUS_REG_ADDR(LCD_PWR_ADDR)
#define P_LCD_PWM0_LO_ADDR 		CBUS_REG_ADDR(LCD_PWM0_LO_ADDR)
#define P_LCD_PWM0_HI_ADDR 		CBUS_REG_ADDR(LCD_PWM0_HI_ADDR)
#define P_LCD_PWM1_LO_ADDR 		CBUS_REG_ADDR(LCD_PWM1_LO_ADDR)
#define P_LCD_PWM1_HI_ADDR 		CBUS_REG_ADDR(LCD_PWM1_HI_ADDR)
#define P_INV_CNT_ADDR 		CBUS_REG_ADDR(INV_CNT_ADDR)
#define P_TCON_MISC_SEL_ADDR 		CBUS_REG_ADDR(TCON_MISC_SEL_ADDR)
#define P_DUAL_PORT_CNTL_ADDR 		CBUS_REG_ADDR(DUAL_PORT_CNTL_ADDR)
#define P_MLVDS_CONTROL 		CBUS_REG_ADDR(MLVDS_CONTROL)
#define P_MLVDS_RESET_PATTERN_HI 		CBUS_REG_ADDR(MLVDS_RESET_PATTERN_HI)
#define P_MLVDS_RESET_PATTERN_LO 		CBUS_REG_ADDR(MLVDS_RESET_PATTERN_LO)
#define P_MLVDS_RESET_PATTERN_EXT 		CBUS_REG_ADDR(MLVDS_RESET_PATTERN_EXT)
#define P_MLVDS_CONFIG_HI 		CBUS_REG_ADDR(MLVDS_CONFIG_HI)
#define P_MLVDS_CONFIG_LO 		CBUS_REG_ADDR(MLVDS_CONFIG_LO)
#define P_TCON_DOUBLE_CTL 		CBUS_REG_ADDR(TCON_DOUBLE_CTL)
#define P_TCON_PATTERN_HI 		CBUS_REG_ADDR(TCON_PATTERN_HI)
#define P_TCON_PATTERN_LO 		CBUS_REG_ADDR(TCON_PATTERN_LO)
#define P_TCON_CONTROL_HI 		CBUS_REG_ADDR(TCON_CONTROL_HI)
#define P_TCON_CONTROL_LO 		CBUS_REG_ADDR(TCON_CONTROL_LO)
#define P_LVDS_BLANK_DATA_HI 		CBUS_REG_ADDR(LVDS_BLANK_DATA_HI)
#define P_LVDS_BLANK_DATA_LO 		CBUS_REG_ADDR(LVDS_BLANK_DATA_LO)
#define P_LVDS_PACK_CNTL_ADDR 		CBUS_REG_ADDR(LVDS_PACK_CNTL_ADDR)
#define P_DE_HS_ADDR 		CBUS_REG_ADDR(DE_HS_ADDR)
#define P_DE_HE_ADDR 		CBUS_REG_ADDR(DE_HE_ADDR)
#define P_DE_VS_ADDR 		CBUS_REG_ADDR(DE_VS_ADDR)
#define P_DE_VE_ADDR 		CBUS_REG_ADDR(DE_VE_ADDR)
#define P_HSYNC_HS_ADDR 		CBUS_REG_ADDR(HSYNC_HS_ADDR)
#define P_HSYNC_HE_ADDR 		CBUS_REG_ADDR(HSYNC_HE_ADDR)
#define P_HSYNC_VS_ADDR 		CBUS_REG_ADDR(HSYNC_VS_ADDR)
#define P_HSYNC_VE_ADDR 		CBUS_REG_ADDR(HSYNC_VE_ADDR)
#define P_VSYNC_HS_ADDR 		CBUS_REG_ADDR(VSYNC_HS_ADDR)
#define P_VSYNC_HE_ADDR 		CBUS_REG_ADDR(VSYNC_HE_ADDR)
#define P_VSYNC_VS_ADDR 		CBUS_REG_ADDR(VSYNC_VS_ADDR)
#define P_VSYNC_VE_ADDR 		CBUS_REG_ADDR(VSYNC_VE_ADDR)
#define P_LCD_MCU_CTL 		CBUS_REG_ADDR(LCD_MCU_CTL)
#define P_LCD_MCU_DATA_0 		CBUS_REG_ADDR(LCD_MCU_DATA_0)
#define P_LCD_MCU_DATA_1 		CBUS_REG_ADDR(LCD_MCU_DATA_1)
#define P_LVDS_GEN_CNTL 		CBUS_REG_ADDR(LVDS_GEN_CNTL)
#define P_LVDS_PHY_CNTL0 		CBUS_REG_ADDR(LVDS_PHY_CNTL0)
#define P_LVDS_PHY_CNTL1 		CBUS_REG_ADDR(LVDS_PHY_CNTL1)
#define P_LVDS_PHY_CNTL2 		CBUS_REG_ADDR(LVDS_PHY_CNTL2)
#define P_LVDS_PHY_CNTL3 		CBUS_REG_ADDR(LVDS_PHY_CNTL3)
#define P_LVDS_PHY_CNTL4 		CBUS_REG_ADDR(LVDS_PHY_CNTL4)
#define P_LVDS_PHY_CNTL5 		CBUS_REG_ADDR(LVDS_PHY_CNTL5)
#define P_LVDS_SRG_TEST 		CBUS_REG_ADDR(LVDS_SRG_TEST)
#define P_LVDS_BIST_MUX0 		CBUS_REG_ADDR(LVDS_BIST_MUX0)
#define P_LVDS_BIST_MUX1 		CBUS_REG_ADDR(LVDS_BIST_MUX1)
#define P_LVDS_BIST_FIXED0 		CBUS_REG_ADDR(LVDS_BIST_FIXED0)
#define P_LVDS_BIST_FIXED1 		CBUS_REG_ADDR(LVDS_BIST_FIXED1)
#define P_LVDS_BIST_CNTL0 		CBUS_REG_ADDR(LVDS_BIST_CNTL0)
#define P_LVDS_CLKB_CLKA 		CBUS_REG_ADDR(LVDS_CLKB_CLKA)
#define P_LVDS_PHY_CLK_CNTL 		CBUS_REG_ADDR(LVDS_PHY_CLK_CNTL)
#define P_LVDS_SER_EN 		CBUS_REG_ADDR(LVDS_SER_EN)
#define P_LVDS_PHY_CNTL6 		CBUS_REG_ADDR(LVDS_PHY_CNTL6)
#define P_LVDS_PHY_CNTL7 		CBUS_REG_ADDR(LVDS_PHY_CNTL7)
#define P_LVDS_PHY_CNTL8 		CBUS_REG_ADDR(LVDS_PHY_CNTL8)
#define P_MLVDS_CLK_CTL_HI 		CBUS_REG_ADDR(MLVDS_CLK_CTL_HI)
#define P_MLVDS_CLK_CTL_LO 		CBUS_REG_ADDR(MLVDS_CLK_CTL_LO)
#define P_MLVDS_DUAL_GATE_WR_START 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_WR_START)
#define P_MLVDS_DUAL_GATE_WR_END 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_WR_END)
#define P_MLVDS_DUAL_GATE_RD_START 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_RD_START)
#define P_MLVDS_DUAL_GATE_RD_END 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_RD_END)
#define P_MLVDS_SECOND_RESET_CTL 		CBUS_REG_ADDR(MLVDS_SECOND_RESET_CTL)
#define P_MLVDS_DUAL_GATE_CTL_HI 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_CTL_HI)
#define P_MLVDS_DUAL_GATE_CTL_LO 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_CTL_LO)
#define P_MLVDS_RESET_CONFIG_HI 		CBUS_REG_ADDR(MLVDS_RESET_CONFIG_HI)
#define P_MLVDS_RESET_CONFIG_LO 		CBUS_REG_ADDR(MLVDS_RESET_CONFIG_LO)
#define P_VPU_OSD1_MMC_CTRL 		CBUS_REG_ADDR(VPU_OSD1_MMC_CTRL)
#define P_VPU_OSD2_MMC_CTRL 		CBUS_REG_ADDR(VPU_OSD2_MMC_CTRL)
#define P_VPU_VD1_MMC_CTRL 		CBUS_REG_ADDR(VPU_VD1_MMC_CTRL)
#define P_VPU_VD2_MMC_CTRL 		CBUS_REG_ADDR(VPU_VD2_MMC_CTRL)
#define P_VPU_DI_IF1_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_IF1_MMC_CTRL)
#define P_VPU_DI_MEM_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_MEM_MMC_CTRL)
#define P_VPU_DI_INP_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_INP_MMC_CTRL)
#define P_VPU_DI_MTNRD_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_MTNRD_MMC_CTRL)
#define P_VPU_DI_CHAN2_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_CHAN2_MMC_CTRL)
#define P_VPU_DI_MTNWR_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_MTNWR_MMC_CTRL)
#define P_VPU_DI_NRWR_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_NRWR_MMC_CTRL)
#define P_VPU_DI_DIWR_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_DIWR_MMC_CTRL)
#define P_VPU_VDIN0_MMC_CTRL 		CBUS_REG_ADDR(VPU_VDIN0_MMC_CTRL)
#define P_VPU_VDIN1_MMC_CTRL 		CBUS_REG_ADDR(VPU_VDIN1_MMC_CTRL)
#define P_VPU_BT656_MMC_CTRL 		CBUS_REG_ADDR(VPU_BT656_MMC_CTRL)
#define P_VPU_TVD3D_MMC_CTRL 		CBUS_REG_ADDR(VPU_TVD3D_MMC_CTRL)
#define P_VPU_TVDVBI_MMC_CTRL 		CBUS_REG_ADDR(VPU_TVDVBI_MMC_CTRL)
#define P_VPU_TVDVBI_VSLATCH_ADDR 		CBUS_REG_ADDR(VPU_TVDVBI_VSLATCH_ADDR)
#define P_VPU_TVDVBI_WRRSP_ADDR 		CBUS_REG_ADDR(VPU_TVDVBI_WRRSP_ADDR)
#define P_VPU_VDIN_PRE_ARB_CTRL 		CBUS_REG_ADDR(VPU_VDIN_PRE_ARB_CTRL)
#define P_VPU_VDISP_PRE_ARB_CTRL 		CBUS_REG_ADDR(VPU_VDISP_PRE_ARB_CTRL)
#define P_VPU_VPUARB2_PRE_ARB_CTRL 		CBUS_REG_ADDR(VPU_VPUARB2_PRE_ARB_CTRL)
#define P_VPU_OSD3_MMC_CTRL 		CBUS_REG_ADDR(VPU_OSD3_MMC_CTRL)
#define P_VPU_OSD4_MMC_CTRL 		CBUS_REG_ADDR(VPU_OSD4_MMC_CTRL)
#define P_VPU_VD3_MMC_CTRL 		CBUS_REG_ADDR(VPU_VD3_MMC_CTRL)
#define P_VPU_VIU_VENC_MUX_CTRL 		CBUS_REG_ADDR(VPU_VIU_VENC_MUX_CTRL)
#define P_VPU_HDMI_SETTING 		CBUS_REG_ADDR(VPU_HDMI_SETTING)
#define P_ENCI_INFO_READ 		CBUS_REG_ADDR(ENCI_INFO_READ)
#define P_ENCP_INFO_READ 		CBUS_REG_ADDR(ENCP_INFO_READ)
#define P_ENCT_INFO_READ 		CBUS_REG_ADDR(ENCT_INFO_READ)
#define P_ENCL_INFO_READ 		CBUS_REG_ADDR(ENCL_INFO_READ)
#define P_AUDIO_COP_CTL2 		CBUS_REG_ADDR(AUDIO_COP_CTL2)
#define P_OPERAND_M_CTL 		CBUS_REG_ADDR(OPERAND_M_CTL)
#define P_OPERAND1_ADDR 		CBUS_REG_ADDR(OPERAND1_ADDR)
#define P_OPERAND2_ADDR 		CBUS_REG_ADDR(OPERAND2_ADDR)
#define P_RESULT_M_CTL 		CBUS_REG_ADDR(RESULT_M_CTL)
#define P_RESULT1_ADDR 		CBUS_REG_ADDR(RESULT1_ADDR)
#define P_RESULT2_ADDR 		CBUS_REG_ADDR(RESULT2_ADDR)
#define P_ADD_SHFT_CTL 		CBUS_REG_ADDR(ADD_SHFT_CTL)
#define P_OPERAND_ONE_H 		CBUS_REG_ADDR(OPERAND_ONE_H)
#define P_OPERAND_ONE_L 		CBUS_REG_ADDR(OPERAND_ONE_L)
#define P_OPERAND_TWO_H 		CBUS_REG_ADDR(OPERAND_TWO_H)
#define P_OPERAND_TWO_L 		CBUS_REG_ADDR(OPERAND_TWO_L)
#define P_RESULT_H 		CBUS_REG_ADDR(RESULT_H)
#define P_RESULT_M 		CBUS_REG_ADDR(RESULT_M)
#define P_RESULT_L 		CBUS_REG_ADDR(RESULT_L)
#define P_WMEM_R_PTR 		CBUS_REG_ADDR(WMEM_R_PTR)
#define P_WMEM_W_PTR 		CBUS_REG_ADDR(WMEM_W_PTR)
#define P_AUDIO_LAYER 		CBUS_REG_ADDR(AUDIO_LAYER)
#define P_AC3_DECODING 		CBUS_REG_ADDR(AC3_DECODING)
#define P_AC3_DYNAMIC 		CBUS_REG_ADDR(AC3_DYNAMIC)
#define P_AC3_MELODY 		CBUS_REG_ADDR(AC3_MELODY)
#define P_AC3_VOCAL 		CBUS_REG_ADDR(AC3_VOCAL)
#define P_ASSIST_AMR_SCRATCH0 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH0)
#define P_ASSIST_AMR_SCRATCH1 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH1)
#define P_ASSIST_AMR_SCRATCH2 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH2)
#define P_ASSIST_AMR_SCRATCH3 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH3)
#define P_ASSIST_HW_REV 		CBUS_REG_ADDR(ASSIST_HW_REV)
#define P_ASSIST_POR_CONFIG 		CBUS_REG_ADDR(ASSIST_POR_CONFIG)
#define P_ASSIST_SPARE16_REG1 		CBUS_REG_ADDR(ASSIST_SPARE16_REG1)
#define P_ASSIST_SPARE16_REG2 		CBUS_REG_ADDR(ASSIST_SPARE16_REG2)
#define P_ASSIST_SPARE8_REG1 		CBUS_REG_ADDR(ASSIST_SPARE8_REG1)
#define P_ASSIST_SPARE8_REG2 		CBUS_REG_ADDR(ASSIST_SPARE8_REG2)
#define P_ASSIST_SPARE8_REG3 		CBUS_REG_ADDR(ASSIST_SPARE8_REG3)
#define P_AC3_CTRL_REG1 		CBUS_REG_ADDR(AC3_CTRL_REG1)
#define P_AC3_CTRL_REG2 		CBUS_REG_ADDR(AC3_CTRL_REG2)
#define P_AC3_CTRL_REG3 		CBUS_REG_ADDR(AC3_CTRL_REG3)
#define P_AC3_CTRL_REG4 		CBUS_REG_ADDR(AC3_CTRL_REG4)
#define P_ASSIST_GEN_CNTL 		CBUS_REG_ADDR(ASSIST_GEN_CNTL)
#define P_AUDIN_SPDIF_MODE 		CBUS_REG_ADDR(AUDIN_SPDIF_MODE)
#define P_AUDIN_SPDIF_FS_CLK_RLTN 		CBUS_REG_ADDR(AUDIN_SPDIF_FS_CLK_RLTN)
#define P_AUDIN_SPDIF_CHNL_STS_A 		CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_A)
#define P_AUDIN_SPDIF_CHNL_STS_B 		CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_B)
#define P_AUDIN_SPDIF_MISC 		CBUS_REG_ADDR(AUDIN_SPDIF_MISC)
#define P_AUDIN_SPDIF_NPCM_PCPD 		CBUS_REG_ADDR(AUDIN_SPDIF_NPCM_PCPD)
#define P_AUDIN_SPDIF_END 		CBUS_REG_ADDR(AUDIN_SPDIF_END)
#define P_AUDIN_I2SIN_CTRL 		CBUS_REG_ADDR(AUDIN_I2SIN_CTRL)
#define P_AUDIN_SOURCE_SEL 		CBUS_REG_ADDR(AUDIN_SOURCE_SEL)
#define P_AUDIN_FIFO0_START 		CBUS_REG_ADDR(AUDIN_FIFO0_START)
#define P_AUDIN_FIFO0_END 		CBUS_REG_ADDR(AUDIN_FIFO0_END)
#define P_AUDIN_FIFO0_PTR 		CBUS_REG_ADDR(AUDIN_FIFO0_PTR)
#define P_AUDIN_FIFO0_INTR 		CBUS_REG_ADDR(AUDIN_FIFO0_INTR)
#define P_AUDIN_FIFO0_RDPTR 		CBUS_REG_ADDR(AUDIN_FIFO0_RDPTR)
#define P_AUDIN_FIFO0_CTRL 		CBUS_REG_ADDR(AUDIN_FIFO0_CTRL)
#define P_AUDIN_FIFO0_CTRL1 		CBUS_REG_ADDR(AUDIN_FIFO0_CTRL1)
#define P_AUDIN_FIFO0_LVL0 		CBUS_REG_ADDR(AUDIN_FIFO0_LVL0)
#define P_AUDIN_FIFO0_LVL1 		CBUS_REG_ADDR(AUDIN_FIFO0_LVL1)
#define P_AUDIN_FIFO0_LVL2 		CBUS_REG_ADDR(AUDIN_FIFO0_LVL2)
#define P_AUDIN_FIFO1_START 		CBUS_REG_ADDR(AUDIN_FIFO1_START)
#define P_AUDIN_FIFO1_END 		CBUS_REG_ADDR(AUDIN_FIFO1_END)
#define P_AUDIN_FIFO1_PTR 		CBUS_REG_ADDR(AUDIN_FIFO1_PTR)
#define P_AUDIN_FIFO1_INTR 		CBUS_REG_ADDR(AUDIN_FIFO1_INTR)
#define P_AUDIN_FIFO1_RDPTR 		CBUS_REG_ADDR(AUDIN_FIFO1_RDPTR)
#define P_AUDIN_FIFO1_CTRL 		CBUS_REG_ADDR(AUDIN_FIFO1_CTRL)
#define P_AUDIN_FIFO1_CTRL1 		CBUS_REG_ADDR(AUDIN_FIFO1_CTRL1)
#define P_AUDIN_FIFO1_LVL0 		CBUS_REG_ADDR(AUDIN_FIFO1_LVL0)
#define P_AUDIN_FIFO1_LVL1 		CBUS_REG_ADDR(AUDIN_FIFO1_LVL1)
#define P_AUDIN_FIFO1_LVL2 		CBUS_REG_ADDR(AUDIN_FIFO1_LVL2)
#define P_AUDIN_FIFO0_REQID 		CBUS_REG_ADDR(AUDIN_FIFO0_REQID)
#define P_AUDIN_FIFO1_REQID 		CBUS_REG_ADDR(AUDIN_FIFO1_REQID)
#define P_AUDIN_INT_CTRL 		CBUS_REG_ADDR(AUDIN_INT_CTRL)
#define P_AUDIN_FIFO_INT 		CBUS_REG_ADDR(AUDIN_FIFO_INT)
#define P_AUDIN_FIFO0_WRAP 		CBUS_REG_ADDR(AUDIN_FIFO0_WRAP)
#define P_AUDIN_FIFO1_WRAP 		CBUS_REG_ADDR(AUDIN_FIFO1_WRAP)
#define P_AUDIN_PIO_STS 		CBUS_REG_ADDR(AUDIN_PIO_STS)
#define P_AUDIN_RD_L 		CBUS_REG_ADDR(AUDIN_RD_L)
#define P_AUDIN_RD_H 		CBUS_REG_ADDR(AUDIN_RD_H)
#define P_PCMIN_CTRL0 		CBUS_REG_ADDR(PCMIN_CTRL0)
#define P_PCMIN_CTRL1 		CBUS_REG_ADDR(PCMIN_CTRL1)
#define P_PCMOUT_CTRL0 		CBUS_REG_ADDR(PCMOUT_CTRL0)
#define P_PCMOUT_CTRL1 		CBUS_REG_ADDR(PCMOUT_CTRL1)
#define P_PCMOUT_CTRL2 		CBUS_REG_ADDR(PCMOUT_CTRL2)
#define P_PCMOUT_CTRL3 		CBUS_REG_ADDR(PCMOUT_CTRL3)
#define P_AUDOUT_CTRL 		CBUS_REG_ADDR(AUDOUT_CTRL)
#define P_AUDOUT_CTRL1 		CBUS_REG_ADDR(AUDOUT_CTRL1)
#define P_AUDOUT_BUF0_STA 		CBUS_REG_ADDR(AUDOUT_BUF0_STA)
#define P_AUDOUT_BUF0_EDA 		CBUS_REG_ADDR(AUDOUT_BUF0_EDA)
#define P_AUDOUT_BUF0_WPTR 		CBUS_REG_ADDR(AUDOUT_BUF0_WPTR)
#define P_AUDOUT_BUF1_STA 		CBUS_REG_ADDR(AUDOUT_BUF1_STA)
#define P_AUDOUT_BUF1_EDA 		CBUS_REG_ADDR(AUDOUT_BUF1_EDA)
#define P_AUDOUT_BUF1_WPTR 		CBUS_REG_ADDR(AUDOUT_BUF1_WPTR)
#define P_AUDOUT_FIFO_RPTR 		CBUS_REG_ADDR(AUDOUT_FIFO_RPTR)
#define P_AUDOUT_INTR_PTR 		CBUS_REG_ADDR(AUDOUT_INTR_PTR)
#define P_AUDOUT_FIFO_STS 		CBUS_REG_ADDR(AUDOUT_FIFO_STS)
#define P_AUDOUT_WR_L 		CBUS_REG_ADDR(AUDOUT_WR_L)
#define P_AUDOUT_WR_H 		CBUS_REG_ADDR(AUDOUT_WR_H)
#define P_AUDIN_ADDR_END 		CBUS_REG_ADDR(AUDIN_ADDR_END)
#endif
